18 December 2014 SOI layout decomposition for double patterning lithography on high-performance computer platforms
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Proceedings Volume 9440, International Conference on Micro- and Nano-Electronics 2014; 94400X (2014) https://doi.org/10.1117/12.2180809
Event: The International Conference on Micro- and Nano-Electronics 2014, 2014, Zvenigorod, Russian Federation
Abstract
In the paper silicon on insulator layout decomposition algorithms for the double patterning lithography on high performance computing platforms are discussed. Our approach is based on the use of a contradiction graph and a modified concurrent breadth-first search algorithm. We evaluate our technique on 45 nm Nangate Open Cell Library including non-Manhattan geometry. Experimental results show that our soft computing algorithms decompose layout successfully and a minimal distance between polygons in layout is increased.
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Vladimir Verstov, Vladimir Verstov, Lyudmila Zinchenko, Lyudmila Zinchenko, Vladimir Makarchuk, Vladimir Makarchuk, } "SOI layout decomposition for double patterning lithography on high-performance computer platforms", Proc. SPIE 9440, International Conference on Micro- and Nano-Electronics 2014, 94400X (18 December 2014); doi: 10.1117/12.2180809; https://doi.org/10.1117/12.2180809
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