18 December 2014 Estimation technique for SET-tolerance of combinational ICs
Author Affiliations +
Proceedings Volume 9440, International Conference on Micro- and Nano-Electronics 2014; 94401A (2014) https://doi.org/10.1117/12.2180608
Event: The International Conference on Micro- and Nano-Electronics 2014, 2014, Zvenigorod, Russian Federation
Abstract
The paper presents an estimation technique for single event transient (SET) tolerance of combinational circuits. Technique provides means to analyze each node contribution to the overall SET tolerance of circuit. A software tool calculates critical charge of each node of circuit, process gathered data and displays it in circuit editor. The technique is technology-independent, it can be applied to nanoscale technologies.
© (2014) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.
A. Balbekov, A. Balbekov, M. Gorbunov, M. Gorbunov, } "Estimation technique for SET-tolerance of combinational ICs", Proc. SPIE 9440, International Conference on Micro- and Nano-Electronics 2014, 94401A (18 December 2014); doi: 10.1117/12.2180608; https://doi.org/10.1117/12.2180608
PROCEEDINGS
7 PAGES


SHARE
Back to Top