21 May 2015 System-on-chip architecture and validation for real-time transceiver optimization: APC implementation on FPGA
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Abstract
New radar applications need to perform complex algorithms and process large quantity of data to generate useful information for the users. This situation has motivated the search for better processing solutions that include low power high-performance processors, efficient algorithms, and high-speed interfaces. In this work, hardware implementation of adaptive pulse compression for real-time transceiver optimization are presented, they are based on a System-on-Chip architecture for Xilinx devices. This study also evaluates the performance of dedicated coprocessor as hardware accelerator units to speed up and improve the computation of computing-intensive tasks such matrix multiplication and matrix inversion which are essential units to solve the covariance matrix. The tradeoffs between latency and hardware utilization are also presented. Moreover, the system architecture takes advantage of the embedded processor, which is interconnected with the logic resources through the high performance AXI buses, to perform floating-point operations, control the processing blocks, and communicate with external PC through a customized software interface. The overall system functionality is demonstrated and tested for real-time operations using a Ku-band tested together with a low-cost channel emulator for different types of waveforms.
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Hernan Suarez, Yan Rockee Zhang, "System-on-chip architecture and validation for real-time transceiver optimization: APC implementation on FPGA", Proc. SPIE 9461, Radar Sensor Technology XIX; and Active and Passive Signatures VI, 946106 (21 May 2015); doi: 10.1117/12.2176839; https://doi.org/10.1117/12.2176839
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