Fast On-Chip Delay Estimation For Cell-Based Emitter Coupled Logic

Peter R. O'Brien; John L. Wyatt Jr.; Thomas L. Savarino; James M. Pierce

doi:10.1117/12.947454

8 September 1988 Fast On-Chip Delay Estimation For Cell-Based Emitter Coupled Logic

Peter R. O'Brien, John L. Wyatt Jr., Thomas L. Savarino, James M. Pierce

Proceedings Volume 0947, Interconnection of High Speed and High Frequency Devices and Systems; (1988) https://doi.org/10.1117/12.947454
Event: Advances in Semiconductors and Superconductors: Physics and Device Applications, 1988, Newport Beach, CA, United States

Abstract

The goal of this work is to produce fast, but accurate, estimates of best and worst case delay for on-chip emitter coupled logic (ECL) nets. The work consists of two major parts: 1) macromodelling of ECL logic gates acting as both sources and loads; and 2) delay estimation for individual nets using the gate macromodel parameters and RC tree models for metal interconnect. Both of the above functions (gate macromodelling and delay estimation) have been extensively tested on an industrial ECL process and.cell (i.e., logic gate) library. The success of a macromodelling approach relies on repet-itive use of members of a library of modelled cells. A "fixed" computational cost (several c.p.u. hours per cell) is paid to obtain simplified macromodel parameter values. Resultant timing estimates are typically within 5-10% of SPICE [1] and are obtained roughly three orders of magnitude more quickly than SPICE.

Citation Download Citation

Peter R. O'Brien, John L. Wyatt Jr., Thomas L. Savarino, and James M. Pierce "Fast On-Chip Delay Estimation For Cell-Based Emitter Coupled Logic", Proc. SPIE 0947, Interconnection of High Speed and High Frequency Devices and Systems, (8 September 1988); https://doi.org/10.1117/12.947454

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