21 May 2015 FPGA-based JPEG-LS encoder for onboard real-time lossless image compression
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In this study, a hardware efficient field-programmable-gate-array (FPGA) implementation of the JPEG-LS encoder for lossless image compression is introduced. Encoder architecture comprises both regular mode and run mode with run interruption sample encoding procedures for full compliance with the ISO/ITU standard. Differently from former reported implementations, prediction error computation is optimized with pipeline data forwarding technique for optimum delay and minimum complexity. Besides, procedures of the run-length encoding are realized with normalization scheme using look-up tables without update latency. Synthesis results showed that proposed optimizations improved the processing speed of the encoder noticeably while FPGA hardware footprint is significantly reduced.
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Yakup Murat Mert, Yakup Murat Mert, "FPGA-based JPEG-LS encoder for onboard real-time lossless image compression", Proc. SPIE 9501, Satellite Data Compression, Communications, and Processing XI, 950106 (21 May 2015); doi: 10.1117/12.2177882; https://doi.org/10.1117/12.2177882

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