13 April 2015 Enhanced memory architecture for massively parallel vision chip
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Proceedings Volume 9522, Selected Papers from Conferences of the Photoelectronic Technology Committee of the Chinese Society of Astronautics 2014, Part II; 95220U (2015) https://doi.org/10.1117/12.2179447
Event: Selected Proceedings of the Photoelectronic Technology Committee Conferences held August-October 2014, 2014, China, China
Abstract
Local memory architecture plays an important role in high performance massively parallel vision chip. In this paper, we propose an enhanced memory architecture with compact circuit area designed in a full-custom flow. The memory consists of separate master-stage static latches and shared slave-stage dynamic latches. We use split transmission transistors on the input data path to enhance tolerance for charge sharing and to achieve random read/write capabilities. The memory is designed in a 0.18 μm CMOS process. The area overhead of the memory achieves 16.6 μm2/bit. Simulation results show that the maximum operating frequency reaches 410 MHz and the corresponding peak dynamic power consumption for a 64-bit memory unit is 190 μW under 1.8 V supply voltage.
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Zhe Chen, Jie Yang, Liyuan Liu, Nanjian Wu, "Enhanced memory architecture for massively parallel vision chip", Proc. SPIE 9522, Selected Papers from Conferences of the Photoelectronic Technology Committee of the Chinese Society of Astronautics 2014, Part II, 95220U (13 April 2015); doi: 10.1117/12.2179447; https://doi.org/10.1117/12.2179447
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