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6 July 2015 Implementation of weighted summation type fractional Fourier transform on FPGA
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Proceedings Volume 9631, Seventh International Conference on Digital Image Processing (ICDIP 2015); 963125 (2015) https://doi.org/10.1117/12.2197111
Event: Seventh International Conference on Digital Image Processing (ICDIP15), 2015, Los Angeles, United States
Abstract
Recently Fractional Fourier transform (FrFT) has got a variety of applications in digital signal and image processing. This paper presents a novel hardware architecture for real-time computation of Discrete Fractional Fourier Transform (DFrFT), which can easily be extended to other fractional transforms. The proposed architecture has been verified on Xilinx FPGA(XC6VLX240T), which can run at a frequency up to 291MHz while with high accuracy.
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Qiming Zou, Longlong Li, Qian Huang, and Fei Wang "Implementation of weighted summation type fractional Fourier transform on FPGA", Proc. SPIE 9631, Seventh International Conference on Digital Image Processing (ICDIP 2015), 963125 (6 July 2015); https://doi.org/10.1117/12.2197111
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