23 October 2015 Lithography and mask challenges at the leading edge
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Abstract
The use of optical multiple patterning, necessitated by persistent delays in the readiness of EUV lithography, has resulted in very little increase in the write time per mask, but there has been a significant increase in the write time for an entire mask set, because of the large increase in the number of masks per set. Although operating lithographic processes near the physical resolution limit of optics, final dimensions continue to scale through the use of multiple patterning, and process control requirements are based on these final dimensions. This results in the need for tight critical dimension control and registration on masks. Although reduction of cost per transistor node-to-node can be continued by the use of multiple patterning, manufacturing cycle times are lengthened appreciably, which has economic impact. With EUV lithography, there are additional mechanisms for overlay errors resulting from non-telecentricity, and corrections will need to be included as part of RET and OPC generation. EUV masks will also need to be very flat or corrections will be required when masks are written. A limited number of small defects can be tolerated on EUV masks by the use of pattern shift methods to cover mask defects with absorber. Interconnect resistance and transistor performance are also significant challenges for enabling future scaling.
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Harry J. Levinson, Harry J. Levinson, } "Lithography and mask challenges at the leading edge", Proc. SPIE 9635, Photomask Technology 2015, 963502 (23 October 2015); doi: 10.1117/12.2203117; https://doi.org/10.1117/12.2203117
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