9 July 2015 High performance ILT for hotspots repair with hierarchical pattern matching
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Inverse lithography technology (ILT) has become one of the key technologies in recent years for highly optimized mask synthesis of physical layout of large scale semiconductor designs. Localized printability enhancement (LPE) has also proved useful in applying computational lithography to repair so-called hotspots to efficiently refine the designs for better process windows without re-optimizing the entire design. Although such a localized design refinement on a relatively small number of hotspots is already quite useful, in reality, it is possible that there are a large number of hotspots, thereby necessitating handling of large volume data in the repair flow. In the case of memory designs, in particular, the number of hotspots in highly repetitive patterns can be enormous, if they are counted from the flattened layout point of view. Since hotspots on repetitive patterns tend to involve processing of repeated patterns, applying pattern matching techniques becomes a natural solution such that only one instance of the repeated patterns is fully re-optimized and its result is copied and pasted over the remaining instances of the same pattern. It is also important to take advantage of the design hierarchy, because flattening of layers in repetitive hierarchical designs can result in data volume expansion that is so massive that even trivial operations such as copying and Boolean operations could become prohibitively slow. We present techniques to exploit pattern matching as well as hierarchical processing to achieve a high performance distributed hotspots reoptimization flow.
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Kyohei Sakajiri, Kyohei Sakajiri, } "High performance ILT for hotspots repair with hierarchical pattern matching ", Proc. SPIE 9658, Photomask Japan 2015: Photomask and Next-Generation Lithography Mask Technology XXII, 96580B (9 July 2015); doi: 10.1117/12.2192929; https://doi.org/10.1117/12.2192929

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