Nowadays, CMOS sensors still suffer from the problem of low SNR, especially in the stage of low illumination and high relative scanning velocity. Lots of methods have been develop to overcome this problem. Among these researches, TDI (Time Delay Integration) architecture is a more natural choice, which is natively supported by CCD sensors. In this paper a new kind of proposed current-mode sensor is used to achieve TDI operation in analog domain. The circuit is composed of three main parts. At first, a current-type pixel is proposed, in which the active MOSFET is operated in the triode region to ensure the output current is linearly dependent on the gate voltage and avoid the reduction of threshold voltage in the traditional voltage mode pixels, such as 3T, 4T which use the source followers as its active part. Then a discrete double sampling (DDS) unit, which is operated in the form of currents is used to efficiently reduce the fixed pattern noise (FPN) and make the output is independent of reset voltage of pixels. For accumulation, an improved current mirror adder under controlled of timing circuits is proposed to overcome the problem of saturation suffered in voltage domain. Some main noise sources, especially come from analog sample and holds capacitors and switches is analyzed. Finally, simulation results with CSMC 0.5um technology and Cadence IC show that the proposed method is reasonable and efficient to improve the SNR.