A 640×512 readout integrated circuit (ROIC) with 15um pixel pitch for middle-wave infrared focal plane arrays (MWIR FPAs) is designed in this paper. The 15um pixel pitch presents several challenges to the ROIC design, such as achieving the required charge storage capacity to preserve the high SNR and reading or processing the pixel signals correctly to achieve the required frame rate. A novel structure that four neighboring pixels share one integration capacitor is presented as a feasible approach to getting a large charge capacity in the limited pixel area. Meanwhile, the pixel circuit chooses the direct injection (DI) which occupies the small layout area as the input stage for MW and contains two sample and hold modules to further increase the charge capacity. Moreover,the peripheral analog signal chain circuit, which is composed of a PMOS source follower, a column amplifier and the complementary output stage, is designed to transfer the signals from unit cell with less voltage loss,lower power consumption, lower noise and higher linearity. More importantly, in our design, only half chain circuit are required therefore the corresponding power consumption will be reduced greatly. In order to accommodate this design, two kinds of pixel signal readout sequences are compared. By adopting the 0.18um 1P6M mixed signal CMOS process, the circuit architecture can make the effective charge capacity of 13Me- per pixel with 1.38V final output range. The 4×4 circuit layout will be fulfilled as a whole and in this way the effective integration capacitor can be increased. According to the simulation results, this circuit works well under 3.3V power supply and achieves 10MHZ readout rate and less than 0.1% nonlinearity.