15 October 2015 Back-side-illuminated 1.4μm pixel with a vertically pinned photodiode based on hole collection, PMOS readout chain and active side-wall passivation
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Proceedings Volume 9674, AOPC 2015: Optical and Optoelectronic Sensing and Imaging Technology; 96742S (2015) https://doi.org/10.1117/12.2202746
Event: Applied Optics and Photonics China (AOPC2015), 2015, Beijing, China
Abstract
To further improve the characteristics of CMOS image sensors (CIS), we propose a back-side illuminated pixel integrating a vertically pinned and P-type photodiode (which collects holes) and PMOS readout circuitry. It has been designed in a 1.4μm-pitch, a two-transistor (2T) shared readout architecture and fabricated in a combined 65nm and 90nm technology. The vertically pinned photodiode takes up almost the entire volume of the pixel, allowing a full well capacity (FWC) exceeding 7000h+. With a conversion factor around 120μV/h+, the output swing approaching 1V is achieved on the column voltage. The pixel also integrates capacitive deep trench isolation (CDTI) to tackle electrical and optical crosstalk issues. The effective passivation of trench interface by CDTI bias control is demonstrated for a hole-based pixel. As expected, PMOS transistors have much lower trapping noise compared to NMOS counterparts. The PMOS source follower has an average temporal noise of 195μV, mainly dominated by thermal noise contribution.
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Bastien Mamdy, Bastien Mamdy, François Roy, François Roy, Nayera Ahmed, Nayera Ahmed, Guo-Neng Lu, Guo-Neng Lu, } "Back-side-illuminated 1.4μm pixel with a vertically pinned photodiode based on hole collection, PMOS readout chain and active side-wall passivation", Proc. SPIE 9674, AOPC 2015: Optical and Optoelectronic Sensing and Imaging Technology, 96742S (15 October 2015); doi: 10.1117/12.2202746; https://doi.org/10.1117/12.2202746
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