This paper describes how to design and develop an advanced Charge Coupled Device (CCD) timing generator which can obtain high precise CCD output signals. Above all, theory of the design and implementation of CCD timing generator is introduced based on Field Programmable Gate Array (FPGA) devices in detail. Secondly, it studies and analyzes the influencing factors that the waveform of CCD driving timing signals have on qualities of CCD output signals, which contain duty-cycle of HCCD clock, positive width of RST, signal-skew and delays among these signals. Then some skills are presented to improve and optimize the design in the phase of coding, compiling and placement and routing, which include code constraint, incremental placement and so on. Finally, simulation and verification of the design are performed with simulation tools, and hardware tests are carried out and experiment results are proved by oscilloscope.