A Model For The Analysis Of Fault-Tolerant Signal Processing Architectures

V. S. S. Nair; J. A. Abraham

doi:10.1117/12.948508

23 February 1988 A Model For The Analysis Of Fault-Tolerant Signal Processing Architectures

V. S. S. Nair, J. A. Abraham

Author Affiliations +

Proceedings Volume 0975, Advanced Algorithms and Architectures for Signal Processing III; (1988) https://doi.org/10.1117/12.948508
Event: 32nd Annual International Technical Symposium on Optical and Optoelectronic Applied Science and Engineering, 1988, San Diego, CA, United States

Abstract

This paper develops a new model, using matrices, for the analysis of fault-tolerant multiprocessor systems. The relationship between processors computing useful data, the output data, and the check processors is defined in terms of matrix entries. Unlike the matrix based models proposed previously for the analysis of digital systems, this model uses only numerical computations rather than logical operations for the analysis of a system. We present algorithms to evaluate the fault detection and location capability of the system. These algorithms are much less complex than the existing ones. We also use the new model to analyze some fault-tolerant architectures proposed for signal processing applications.

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V. S. S. Nair and J. A. Abraham "A Model For The Analysis Of Fault-Tolerant Signal Processing Architectures", Proc. SPIE 0975, Advanced Algorithms and Architectures for Signal Processing III, (23 February 1988); https://doi.org/10.1117/12.948508

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