Translator Disclaimer
15 March 2016 Low-power chip-level optical interconnects based on bulk-silicon single-chip photonic transceivers
Author Affiliations +
Proceedings Volume 9753, Optical Interconnects XVI; 975315 (2016)
Event: SPIE OPTO, 2016, San Francisco, California, United States
We present new scheme for chip-level photonic I/Os, based on monolithically integrated vertical photonic devices on bulk silicon, which increases the integration level of PICs to a complete photonic transceiver (TRx) including chip-level light source. A prototype of the single-chip photonic TRx based on a bulk silicon substrate demonstrated 20 Gb/s low power chip-level optical interconnects between fabricated chips, proving that this scheme can offer compact low-cost chip-level I/O solutions and have a significant impact on practical electronic-photonic integration in high performance computers (HPC), cpu-memory interface, 3D-IC, and LAN/SAN/data-center and network applications.
© (2016) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.
Gyungock Kim, Hyundai Park, Jiho Joo, Ki-Seok Jang, Myung-Joon Kwack, Sanghoon Kim, In Gyoo Kim, Sun Ae Kim, Jin Hyuk Oh, Jaegyu Park, and Sanggi Kim "Low-power chip-level optical interconnects based on bulk-silicon single-chip photonic transceivers", Proc. SPIE 9753, Optical Interconnects XVI, 975315 (15 March 2016);

Back to Top