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1 April 2016 Sub-10nm lines and spaces patterning using grapho-epitaxial directed self-assembly of lamellar block copolymers
Yuriko Seino; Hironobu Sato; Yusuke Kasahara; Shinya Minegishi; Ken Miyagi; Hitoshi Kubota; Hideki Kanai; Katsuyoshi Kodera; Masayuki Shiraishi; Naoko Kihara; Yoshiaki Kawamonzen; Toshikatsu Tobana; Katsutoshi Kobayashi; Hitoshi Yamano; Tsukasa Azuma; Satoshi Nomura
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Proceedings Volume 9777, Alternative Lithographic Technologies VIII; 97771T (2016) https://doi.org/10.1117/12.2218787
Event: SPIE Advanced Lithography, 2016, San Jose, California, United States
Abstract
Our target at EIDEC is to study the feasibility of directed self-assembly (DSA) technology for semiconductor device manufacturing through electrical yield verification by development of such as process, material, metrology, simulation and design for DSA. We previously developed a grapho/chemo-hybrid coordinated line epitaxial process for sub-15-nm line-and-space (L/S) patterning using polystyrene-block-poly(methyl methacrylate) lamellar block copolymers (BCPs)1– 3. Electrical yield verification results showed that a 30% open yield was successfully achieved with a metal wire line length of 700 μm 4. In the next stage of the evaluation, a sub-10-nm L/S DSA patterning process based on graphoepitaxial DSA of 20-nm lamellar period organic BCPs was developed based on neutral layer and guide space width optimization. At a 30-nm guide height, problems such as BCP overflow and DSA line shorts were observed after the dry development. At a 60-nm guide height, grid-like short defects were observed under dry development shallow etch conditions and sub-10-nm L/S patterns were formed under optimized etch conditions with a suitable BCP film thickness margin. The process performance was evaluated in terms of defects and critical dimension measurements using an electron beam inspection system and critical dimension-scanning electron microscope metrology. The main DSA defects were short defects, and the spatial roughness appeared to be caused by the periodic pitches of these short defects and the guide roughness. We successfully demonstrated the fabrication of sub-10-nm metal wires consists of L/S, pad, connect and cut patterns with controlled alignment and stack structure through lithography, etching and CMP process on a 300- mm wafer using the fully integrated DSA process and damascene processing.
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Yuriko Seino, Yuriko Seino, Hironobu Sato, Hironobu Sato, Yusuke Kasahara, Yusuke Kasahara, Shinya Minegishi, Shinya Minegishi, Ken Miyagi, Ken Miyagi, Hitoshi Kubota, Hitoshi Kubota, Hideki Kanai, Hideki Kanai, Katsuyoshi Kodera, Katsuyoshi Kodera, Masayuki Shiraishi, Masayuki Shiraishi, Naoko Kihara, Naoko Kihara, Yoshiaki Kawamonzen, Yoshiaki Kawamonzen, Toshikatsu Tobana, Toshikatsu Tobana, Katsutoshi Kobayashi, Katsutoshi Kobayashi, Hitoshi Yamano, Hitoshi Yamano, Tsukasa Azuma, Tsukasa Azuma, Satoshi Nomura, Satoshi Nomura, } "Sub-10nm lines and spaces patterning using grapho-epitaxial directed self-assembly of lamellar block copolymers", Proc. SPIE 9777, Alternative Lithographic Technologies VIII, 97771T (1 April 2016); doi: 10.1117/12.2218787; https://doi.org/10.1117/12.2218787
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