With the continuous shrink of design rules from 14nm to 10nm to 7nm, conserving process windows in a high volume manufacturing environment is becoming more and more difficult. Masks, scanners, and etch processes have to meet very tight specifications in order to keep defect, CD, as well as overlay within the margins of the process window. In this work, we study a design-based e-beam defect inspection technology for wafer level process window characterization and intra-field defect variability on 10nm logic devices. Due to high resolution, e-beam technology is the natural choice for review and/or detection of subtle pattern deviations, aka defects. The capability of integrating design information (GDS file) with defect detection, dimension measurement of critical structure, and defect classification provides added values for engineers to identify yield limiting systematic defects and to provide feedback to design.