20 October 2016 Eliminating the offset between overlay metrology and device patterns using computational metrology target design
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Abstract
Designing metrology targets that mimic process device cell behavior is becoming a common component in overlay process control. For an advanced DRAM process (sub 20 nm node), the extreme illumination methods needed to pattern the critical device features makes it harder to control the aberration induced overlay delta between metrology target and device patterns. To compensate for this delta, a Non-Zero-Offset is applied to the metrology measurement that is based on a manual calibration measurement using CD-SEM Overlay. In this paper, we document how this mismatch can be minimized through the right choice of metrology targets and measurement recipe.
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Jianming Zhou, Jianming Zhou, Sarah Wu, Sarah Wu, Craig Hickman, Craig Hickman, Ewoud van West, Ewoud van West, Maurits van der Schaar, Maurits van der Schaar, Wangshi Zhou, Wangshi Zhou, Youping Zhang, Youping Zhang, Sean Park, Sean Park, Paul Tuffy, Paul Tuffy, Dan Ulmer, Dan Ulmer, Cedric Affentauschegg, Cedric Affentauschegg, Henk Niesing, Henk Niesing, "Eliminating the offset between overlay metrology and device patterns using computational metrology target design", Proc. SPIE 9778, Metrology, Inspection, and Process Control for Microlithography XXX, 97781G (20 October 2016); doi: 10.1117/12.2219439; https://doi.org/10.1117/12.2219439
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