24 March 2016 OPC optimization techniques for enabling the reduction of mismatch between overlay metrology and the device pattern cell
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Abstract
Aberration sensitivity matching between overlay metrology targets and the device cell pattern has become a common requirement on the latest DRAM process nodes. While the extreme illumination modes used demand that the delta in aberration sensitivity must be optimized, it is effectively limited by the ability to print an optimum target that will meet detectability and accuracy requirements. Therefore, advanced OPC techniques are required to ensure printability and have optimal detectability performance while maintaining sufficient process window to avoid patterning or defectivity issues.

In this paper, we have compared various mark designs with real cell in terms of aberration sensitivity under the specific illumination condition. The specific illumination model was used for aberration sensitivity simulation while varying mask tones and target designs. Then, diffraction based simulation was conducted to analyze the effect of aberration sensitivity on the actual overlay values. The simulation results were confirmed by comparing the OL results obtained by diffraction based metrology with the cell level OL values obtained using Critical Dimension Scanning Electron Microscope.
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Shinyoung Kim, Chanha Park, Jinhyuck Jun, Jaehee Hwang, Hyunjo Yang, Nang-Lyeom Oh, Sean Park, Chris Park, Kyu-Tae Sun, Youping Zhang, Paul Tuffy, "OPC optimization techniques for enabling the reduction of mismatch between overlay metrology and the device pattern cell", Proc. SPIE 9778, Metrology, Inspection, and Process Control for Microlithography XXX, 97781S (24 March 2016); doi: 10.1117/12.2219467; https://doi.org/10.1117/12.2219467
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