18 March 2016 Advanced overlay: sampling and modeling for optimized run-to-run control
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Proceedings Volume 9778, Metrology, Inspection, and Process Control for Microlithography XXX; 97782K (2016); doi: 10.1117/12.2218729
Event: SPIE Advanced Lithography, 2016, San Jose, California, United States
Abstract
In recent years overlay (OVL) control schemes have become more complicated in order to meet the ever shrinking margins of advanced technology nodes. As a result, this brings up new challenges to be addressed for effective run-to- run OVL control. This work addresses two of these challenges by new advanced analysis techniques: (1) sampling optimization for run-to-run control and (2) bias-variance tradeoff in modeling. The first challenge in a high order OVL control strategy is to optimize the number of measurements and the locations on the wafer, so that the “sample plan” of measurements provides high quality information about the OVL signature on the wafer with acceptable metrology throughput. We solve this tradeoff between accuracy and throughput by using a smart sampling scheme which utilizes various design-based and data-based metrics to increase model accuracy and reduce model uncertainty while avoiding wafer to wafer and within wafer measurement noise caused by metrology, scanner or process. This sort of sampling scheme, combined with an advanced field by field extrapolated modeling algorithm helps to maximize model stability and minimize on product overlay (OPO). Second, the use of higher order overlay models means more degrees of freedom, which enables increased capability to correct for complicated overlay signatures, but also increases sensitivity to process or metrology induced noise. This is also known as the bias-variance trade-off. A high order model that minimizes the bias between the modeled and raw overlay signature on a single wafer will also have a higher variation from wafer to wafer or lot to lot, that is unless an advanced modeling approach is used. In this paper, we characterize the bias-variance trade off to find the optimal scheme. The sampling and modeling solutions proposed in this study are validated by advanced process control (APC) simulations to estimate run-to-run performance, lot-to-lot and wafer-to- wafer model term monitoring to estimate stability and ultimately high volume manufacturing tests to monitor OPO by densely measured OVL data.
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Lokesh Subramany, WoongJae Chung, Pavan Samudrala, Haiyong Gao, Nyan Aung, Juan Manuel Gomez, Karsten Gutjahr, DongSuk Park, Patrick Snow, Miguel Garcia-Medina, Lipkong Yap, Onur Nihat Demirer, Bill Pierson, John C. Robinson, "Advanced overlay: sampling and modeling for optimized run-to-run control", Proc. SPIE 9778, Metrology, Inspection, and Process Control for Microlithography XXX, 97782K (18 March 2016); doi: 10.1117/12.2218729; https://doi.org/10.1117/12.2218729
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KEYWORDS
Semiconducting wafers

Overlay metrology

Data modeling

Metrology

Scanners

Mathematical modeling

Process control

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