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24 March 2016 Improving scanner wafer alignment performance by target optimization
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In the process nodes of 10nm and below, the patterning complexity along with the processing and materials required has resulted in a need to optimize alignment targets in order to achieve the required precision, accuracy and throughput performance. Recent industry publications on the metrology target optimization process have shown a move from the expensive and time consuming empirical methodologies, towards a faster computational approach. ASML’s Design for Control (D4C) application, which is currently used to optimize YieldStar diffraction based overlay (DBO) metrology targets, has been extended to support the optimization of scanner wafer alignment targets. This allows the necessary process information and design methodology, used for DBO target designs, to be leveraged for the optimization of alignment targets. In this paper, we show how we applied this computational approach to wafer alignment target design. We verify the correlation between predictions and measurements for the key alignment performance metrics and finally show the potential alignment and overlay performance improvements that an optimized alignment target could achieve.
© (2016) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.
Philippe Leray, Christiane Jehoul, Robert Socha, Boris Menchtchikov, Sudhar Raghunathan, Eric Kent, Hielke Schoonewelle, Patrick Tinnemans, Paul Tuffy, Jun Belen, and Rich Wise "Improving scanner wafer alignment performance by target optimization", Proc. SPIE 9778, Metrology, Inspection, and Process Control for Microlithography XXX, 97782M (24 March 2016);

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