8 March 2016 Metrology target design (MTD) solution for diagonally orientated DRAM layer
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Abstract
We present a novel metrology target design framework using the scanner exit pupil wavefront analysis together with Zernike sensitivity analysis (ZSA) based on the Monte-Carlo technique. The proposed method enables the design of robust metrology targets that maximize target process window (PW) while minimizing placement error discrepancies with device features in the presence of spatial and temporal variation of the aberration characteristics of an exposure tool. Knowing the limitations of lithography systems, design constraints, and detailed lithography information including illumination, mask type, etc., we can successfully design an optimal metrology target. We have validated our new metrology target design (MTD) method for one of the challenging DRAM active layer consisting of diagonal line and space patterns illuminated by a rotated extreme dipole source. We find that an optimal MTD target gives the maximized PW and the strong device correlation, resulting in the dramatic improvement of overall overlay performance. The proposed target design framework is completely general and can be used to optimize targets for different lithography conditions. The results from our analysis are both physically sensible and in good agreement with experimental results.
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Myungjun Lee, Myungjun Lee, Mark D. Smith, Mark D. Smith, Michael E. Adel, Michael E. Adel, Chia-Hung Chen, Chia-Hung Chen, Chin-Chang Huang, Chin-Chang Huang, Hao-Lun Huang, Hao-Lun Huang, Hsueh-Jen Tsai, Hsueh-Jen Tsai, I-Lin Wang, I-Lin Wang, Jen-Chou Huang, Jen-Chou Huang, Jo-Lan Chin, Jo-Lan Chin, Kuo-Yao Chou, Kuo-Yao Chou, Yuan-Ku Lan, Yuan-Ku Lan, Hsien-Yen Lung, Hsien-Yen Lung, Jui-Chin Yang, Jui-Chin Yang, Tal Itzkovich, Tal Itzkovich, Healthy Huang, Healthy Huang, Yaniv Abramovitz, Yaniv Abramovitz, Jinyan Song, Jinyan Song, Chen Dror, Chen Dror, Harvey Cheng, Harvey Cheng, Ady Levy, Ady Levy, "Metrology target design (MTD) solution for diagonally orientated DRAM layer", Proc. SPIE 9778, Metrology, Inspection, and Process Control for Microlithography XXX, 97782R (8 March 2016); doi: 10.1117/12.2218659; https://doi.org/10.1117/12.2218659
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