As design rules for leading edge devices have shrunk to 1x nm size and below, device patterns have become sensitive to sub-10nm size defects. Additionally, defectivity and yield are now increasingly dominated by systematic patterning defects. A method for identifying and inspecting these hot spot (HS) locations is necessary for both technology development and High Volume Manufacturing (HVM). In order to achieve sufficient statistical significance across the wafer for a specific product and layer, a guided, high-speed e-beam inspection system is needed to cover a significant amount of high-volume hot spot locations for process window monitoring. In this paper, we explore the capabilities of a novel, highthroughput e-beam hot spot inspection tool, SkyScanTM 5000, on a 10nm back-end-of-line (BEOL) wafer patterned using a triple lithography-etch process. ASML’s high-resolution, design-aware computational hot spot inspection is used to identify relevant hot spot locations, including overlay-sensitive patterns. We guide the e-beam tool to these Points of Interest (POI) and obtain experimental data from inspection of 430k wafer locations. The large amount of data allows detection of wafer-level and intra-field defect signatures for a large number of hot spot patterns.