A novel classification methodology is constructed for Electron Beam (E-Beam) die-to-database (D2DB) inspection results on contact and via layers. It is a design guided defects classification flow that helps to pin-point true defects from a large amount of false alarm defects. Die-to-database E-beam inspection has remarkable features that can help find systematic defects such as Damaged Via and Missing Via; which will be reported as DVC (Dark Voltage Contrast) defects. However, the D2DB result usually reports millions of defects that lie on both ‘active via’ and ‘floating via’, the former being defects-of-interest (DOI), and the latter being of little significance. The indiscriminant mixture of DOI (on active vias) and nuisance (on floating vias) is a challenge in the use of D2DB for finding systematic via defects. We overcome this challenge by overlaying the E-beam defect location onto the design layout file (GDS or OASIS) and tracing the path of the via to determine whether or not it connects to the active or diffusion layer. Our proposed flow uses Net Tracing Classification (NTC) feature in Anchor Hotspot Solution (AHS) to classify all the reported DVC defects into different groups, according to the electrical connectivity of the contact. This classification involves multiple interconnected process layers. All the reported DVC defects will be classified into three groups: (1) Real DVC defects, in which the net traces down to active layer; (2) False DVC type 1, in which the net traces down to gate (which is always dark); (3) False DVC type 2, in which the net traces down to floating metal (which is always dark as well). This enhanced defect classification is greatly helpful in separating real DVC contact/via defects from false alarms. It has a secondary benefit of reducing the total number of defects, which is helpful for subsequent in-depth data analysis. In addition, the verified real DVC locations can be used to generate care areas for E-Beam die-to-die (D2D) inspection, which can effectively improve throughput and reduce the turn-around-time (TAT). In this paper, we will discuss a use case at the Vx layer.