25 March 2016 Contact/Via placement management for N7 logic and beyond
Author Affiliations +
The continuously scaling of complex device geometries is driving by the self-aligned multiple patterning techniques. Depending on such simplified LS scaling, FinFET design rule has been accelerated to unidirectional design layout. [1] In particular Fin, Gate and Metal layers are based on grating with cutting/blocking scheme, these process have become high volume manufacturing techniques in N14 and beyond.[2,3] On the other hand, immersions based pitch scaling of contact hole, via and cutmask processes are required multiple lithography and etching passes.[4] Overlay management is not only the overlay accuracy of layer to layer, to determine the placement error and patterning fidelity in single layer. In this work, focusing on the placement in hole pattern, total placement error budget will be discussed from the viewpoints of metrology, inspection, Mask, OPC and wafer processing. In addition, hole shrink and hole healing techniques have more significant factors in terms of design-process technology co-optimization for N7 and beyond.[5]
© (2016) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.
Kenichi Oyama, Kenichi Oyama, Arisa Hara, Arisa Hara, Kyohei Koike, Kyohei Koike, Masatoshi Yamato, Masatoshi Yamato, Shohei Yamauchi, Shohei Yamauchi, Sakurako Natori, Sakurako Natori, Hidetami Yaegashi, Hidetami Yaegashi, "Contact/Via placement management for N7 logic and beyond", Proc. SPIE 9779, Advances in Patterning Materials and Processes XXXIII, 97790M (25 March 2016); doi: 10.1117/12.2218976; https://doi.org/10.1117/12.2218976


Patterning options for N7 logic prospects and challenges for...
Proceedings of SPIE (September 03 2015)
CD bias control on hole pattern
Proceedings of SPIE (March 24 2016)
170 nm gates fabricated by phase shift mask and top...
Proceedings of SPIE (August 07 1993)

Back to Top