25 March 2016 A physical resist shrinkage model for full-chip lithography simulations
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Abstract
Strong resist shrinkage effects have been widely observed in resist profiles after negative tone development (NTD) and therefore must be taken into account in computational lithography applications. However, existing lithography simulation tools, especially those designed for full-chip applications, lack resist shrinkage modeling capabilities because they are not needed until only recently when NTD processes begin to replace the conventional positive tone development (PTD) processes where resist shrinkage effects are negligible. In this work we describe the development of a physical resist shrinkage (PRS) model for full-chip lithography simulations and present its accuracy evaluation against experimental data.
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Peng Liu, Peng Liu, Leiwu Zheng, Leiwu Zheng, Maggie Ma, Maggie Ma, Qian Zhao, Qian Zhao, Yongfa Fan, Yongfa Fan, Qiang Zhang, Qiang Zhang, Mu Feng, Mu Feng, Xin Guo, Xin Guo, Tom Wallow, Tom Wallow, Keith Gronlund, Keith Gronlund, Ronald Goossens, Ronald Goossens, Gary Zhang, Gary Zhang, Yenwen Lu, Yenwen Lu, } "A physical resist shrinkage model for full-chip lithography simulations", Proc. SPIE 9779, Advances in Patterning Materials and Processes XXXIII, 97790Y (25 March 2016); doi: 10.1117/12.2239243; https://doi.org/10.1117/12.2239243
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