Computational process modeling and correction in a multi-patterning era

Chris Spence

doi:10.1117/12.2225456

Translator Disclaimer

15 March 2016 Computational process modeling and correction in a multi-patterning era

Chris Spence

Author Affiliations +

Proceedings Volume 9780, Optical Microlithography XXIX; 978005 (2016) https://doi.org/10.1117/12.2225456
Event: SPIE Advanced Lithography, 2016, San Jose, California, United States

Abstract

Since the 28nm node, the resolution of ArFi lithography tools has been limited by the fixed Numerical Aperture of the scanners (1.35) at approximately 40-45 nm half-pitch. As a consequence, the shrink cadence identified by Moore’s law requires more complex patterning flows such as multiple Litho-Etch (LE) steps as well as spacer techniques (Self-Aligned Double Patterning (SADP)). To ensure yield it is necessary to optimize the total Edge Placement Error, a combination of Overlay, Global CDU, LCDU, OPC and other process and equipment errors.

In this presentation I will discuss some of the ways that these contributors can be measured, modeled and corrected as part of a Holistic Lithography methodology. Multiple-patterning techniques can be combined with EUV lithography to continue Moore’s law down to final pattern dimensions of 5-6 nm half pitch.

Citation Download Citation

Chris Spence "Computational process modeling and correction in a multi-patterning era", Proc. SPIE 9780, Optical Microlithography XXIX, 978005 (15 March 2016); https://doi.org/10.1117/12.2225456

ACCESS THE FULL ARTICLE