In this paper, overlay budget break was performed prior to experiments with the purpose of estimating amount of overlay improvement. And wafer to wafer correction was simulated to the specified layer of a 2x node DRAM device. As a result, not only maximum 94.4% of residual variation improvement is estimated, but also recognized that more samplings to cover all wafer’s behavior is inevitable. Integrated metrology with optimized sampling scheme was also introduced as a supportive method for more samplings.
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Young Sin Choi, Young Sun Nam, Dong Han Lee, Jae Il Lee, Young Seog Kang, Se Yeon Jang, Jeong Heung Kong, "Intra-lot wafer by wafer overlay control using integrated and standalone metrology combined sampling," Proc. SPIE 9780, Optical Microlithography XXIX, 978009 (15 March 2016);