15 March 2016 Reduction of wafer-edge overlay errors using advanced correction models, optimized for minimal metrology requirements
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Abstract
In order to optimize yield in DRAM semiconductor manufacturing for 2x nodes and beyond, the (processing induced) overlay fingerprint towards the edge of the wafer needs to be reduced. Traditionally, this is achieved by acquiring denser overlay metrology at the edge of the wafer, to feed field-by-field corrections. Although field-by-field corrections can be effective in reducing localized overlay errors, the requirement for dense metrology to determine the corrections can become a limiting factor due to a significant increase of metrology time and cost. In this study, a more cost-effective solution has been found in extending the regular correction model with an edge-specific component. This new overlay correction model can be driven by an optimized, sparser sampling especially at the wafer edge area, and also allows for a reduction of noise propagation. Lithography correction potential has been maximized, with significantly less metrology needs. Evaluations have been performed, demonstrating the benefit of edge models in terms of on-product overlay performance, as well as cell based overlay performance based on metrology-to-cell matching improvements. Performance can be increased compared to POR modeling and sampling, which can contribute to (overlay based) yield improvement. Based on advanced modeling including edge components, metrology requirements have been optimized, enabling integrated metrology which drives down overall metrology fab footprint and lithography cycle time.
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Min-Suk Kim, Min-Suk Kim, Hwa-Yeon Won, Hwa-Yeon Won, Jong-Mun Jeong, Jong-Mun Jeong, Paul Böcker, Paul Böcker, Lydia Vergaij-Huizer, Lydia Vergaij-Huizer, Michiel Kupers, Michiel Kupers, Milenko Jovanović, Milenko Jovanović, Inez Sochal, Inez Sochal, Kevin Ryan, Kevin Ryan, Kyu-Tae Sun, Kyu-Tae Sun, Young-Wan Lim, Young-Wan Lim, Jin-Moo Byun, Jin-Moo Byun, Gwang-Gon Kim, Gwang-Gon Kim, Jung-Joon Suh, Jung-Joon Suh, } "Reduction of wafer-edge overlay errors using advanced correction models, optimized for minimal metrology requirements", Proc. SPIE 9780, Optical Microlithography XXIX, 97800A (15 March 2016); doi: 10.1117/12.2220459; https://doi.org/10.1117/12.2220459
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