15 March 2016 Patterned wafer geometry (PWG) metrology for improving process-induced overlay and focus problems
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Abstract
Prime silicon wafers are ideal substrates for lithographic patterning, with tight flatness specifications for focus control. Process engineers are painfully aware that in-process product wafers can substantially depart from this ideal substrate. Wafer processing can induce non-flatness leading to focus problems, or distort the wafer leading to overlay issues. Thus processes from outside the lithography sector can impact yield by ruining lithographic pattern quality. Double-sided optical interferometric metrology is the standard method to assess the flatness of blank silicon wafers. In the last several years, a similar Patterned Wafer Geometry (PWG) metrology tool is able to measure in-process patterned wafers. The apparent surface seen by an interferometer may be different than the true surface due to transparent thin films, a discrepancy that we call "false topography". Modeling results will demonstrate the use of a thin opaque film to reduce the problem. PWG metrology offers compelling advantages for the practical investigation of process-induced focus and overlay problems. The paper will include several examples of process learning from PWG metrology.
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Timothy A. Brunner, Timothy A. Brunner, Yue Zhou, Yue Zhou, Cheuk W. Wong, Cheuk W. Wong, Bradley Morgenfeld, Bradley Morgenfeld, Gerald Leino, Gerald Leino, Sunit Mahajan, Sunit Mahajan, "Patterned wafer geometry (PWG) metrology for improving process-induced overlay and focus problems", Proc. SPIE 9780, Optical Microlithography XXIX, 97800W (15 March 2016); doi: 10.1117/12.2218630; https://doi.org/10.1117/12.2218630
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