15 March 2016 Simple method for decreasing wafer topography effect for implant mask
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Proceedings Volume 9780, Optical Microlithography XXIX; 97801E (2016); doi: 10.1117/12.2219863
Event: SPIE Advanced Lithography, 2016, San Jose, California, United States
Abstract
Controlling critical dimension (CD) of implant blocking layers during photolithography has been challenging due to reflection caused by wafer topography. Unexpected reflection which comes from wafer topography makes severe CD variation on mask patterns of implant layer. Using bottom antireflective coatings(BARCs) can reduce the topography effect, but it could also damage wafer surface during BARCs dry etching. Developable BARCs(D-BARCs) could be alternative solution for wafer topography effect. However there are some issues that should be considered in D-BARCs process such as sensitive temperature control and managing defects. There are also papers introducing model based topography aware OPC as a solution for wafer topography effect implant layer. But building topography aware OPC model is very complex and it takes too much time to build.

In this paper, we will introduce experimental results of wafer topography effect using various test patterns and propose a simple method that could effectively reduce wafer topography effect.
© (2016) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.
Taejun You, Taehyeong Lee, Gyun Yoo, Youngjoon Park, Cheolkyun Kim, Donggyu Yim, "Simple method for decreasing wafer topography effect for implant mask", Proc. SPIE 9780, Optical Microlithography XXIX, 97801E (15 March 2016); doi: 10.1117/12.2219863; http://dx.doi.org/10.1117/12.2219863
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KEYWORDS
Semiconducting wafers

Critical dimension metrology

Photomasks

Optical proximity correction

Data modeling

Reflection

Visualization

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