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15 March 2016 OPC for curved designs in application to photonics on silicon
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Today's design for photonics devices on silicon relies on non-Manhattan features such as curves and a wide variety of angles with minimum feature size below 100nm. Industrial manufacturing of such devices requires optimized process window with 193nm lithography. Therefore, Resolution Enhancement Techniques (RET) that are commonly used for CMOS manufacturing are required.

However, most RET algorithms are based on Manhattan fragmentation (0°, 45° and 90°) which can generate large CD dispersion on masks for photonic designs. Industrial implementation of RET solutions to photonic designs is challenging as most currently available OPC tools are CMOS-oriented. Discrepancy from design to final results induced by RET techniques can lead to lower photonic device performance.

We propose a novel sizing algorithm allowing adjustment of design edge fragments while preserving the topology of the original structures. The results of the algorithm implementation in the rule based sizing, SRAF placement and model based correction will be discussed in this paper. Corrections based on this novel algorithm were applied and characterized on real photonics devices. The obtained results demonstrate the validity of the proposed correction method integrated in Inscale software of Aselta Nanographics.
© (2016) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.
Bastien Orlando, Vincent Farys, Loïc Schneider, Sébastien Cremer, Sergei V. Postnikov, Matthieu Millequant, Mathieu Dirrenberger, Charles Tiphine, Sébastian Bayle, Céline Tranquillin, and Patrick Schiavone "OPC for curved designs in application to photonics on silicon", Proc. SPIE 9780, Optical Microlithography XXIX, 97801U (15 March 2016);

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