16 March 2016 Methodology to extract, data mine and score geometric constructs from physical design layouts for analysis and applications in semiconductor manufacturing
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Abstract
At advanced technology nodes (sub-22 nm), design rules become very complicated as interactions between multiple layers become more complex, while the number of design elements within the optical radius increases. As a result, one may possibly encounter novel yield limiters in the 2D/3D design space with every new product taping out to the fab. Key to fast yield ramp is identifying novel constructs that may become yield detractors, and to address the challenge in the DFM space before actual Silicon is run. A comprehensive methodology to find such geometric constructs is proposed.
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Piyush Pathak, Karthik Krishnamoorthy, Wei-Long Wang, Ya-Chieh Lai, Frank E. Gennari, Shikha Somani, Bob Pack, Uwe Paul Schroeder, Fadi Batarseh, Jaime Bravo, Jason Sweis, Philippe Hurat, Sriram Madhavan, "Methodology to extract, data mine and score geometric constructs from physical design layouts for analysis and applications in semiconductor manufacturing", Proc. SPIE 9781, Design-Process-Technology Co-optimization for Manufacturability X, 978109 (16 March 2016); doi: 10.1117/12.2220145; https://doi.org/10.1117/12.2220145
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