This paper presents a novel method of how to generate test key patterns which contain known problematic patterns as well as any constructs which designers could possibly draw based on current design rules. The enumerated test key patterns will contain the most critical design structures which are allowed by any particular design rule. A layout profiling method is used to do design chip analysis in order to find potential weak points on new incoming products so fab can take preemptive action to avoid yield loss. It can be achieved by comparing different products and leveraging the knowledge learned from previous manufactured chips to find possible yield detractors.
ACCESS THE FULL ARTICLE
Linda Zhuang, Jenny Pang, Jessy Xu, Mengfeng Tsai, Amy Wang, Yifan Zhang, Jason Sweis, Ya-Chieh Lai, Hua Ding, "Using pattern enumeration to accelerate process development and ramp yield," Proc. SPIE 9781, Design-Process-Technology Co-optimization for Manufacturability X, 97810A (16 March 2016);