Variability-aware compact modeling and statistical circuit validation on SRAM test array

Ying Qiao; Costas J. Spanos

doi:10.1117/12.2219428

16 March 2016 Variability-aware compact modeling and statistical circuit validation on SRAM test array

Ying Qiao, Costas J. Spanos

Proceedings Volume 9781, Design-Process-Technology Co-optimization for Manufacturability X; 97810D (2016) https://doi.org/10.1117/12.2219428
Event: SPIE Advanced Lithography, 2016, San Jose, California, United States

Abstract

Variability modeling at the compact transistor model level can enable statistically optimized designs in view of limitations imposed by the fabrication technology. In this work we propose a variability-aware compact model characterization methodology based on stepwise parameter selection. Transistor I-V measurements are obtained from bit transistor accessible SRAM test array fabricated using a collaborating foundry’s 28nm FDSOI technology. Our in-house customized Monte Carlo simulation bench can incorporate these statistical compact models; and simulation results on SRAM writability performance are very close to measurements in distribution estimation. Our proposed statistical compact model parameter extraction methodology also has the potential of predicting non-Gaussian behavior in statistical circuit performances through mixtures of Gaussian distributions.

Citation Download Citation

Ying Qiao and Costas J. Spanos "Variability-aware compact modeling and statistical circuit validation on SRAM test array", Proc. SPIE 9781, Design-Process-Technology Co-optimization for Manufacturability X, 97810D (16 March 2016); https://doi.org/10.1117/12.2219428

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