In this paper we present a hotspot detection and removal/prevention flow. The flow uses Cadence Design System’s manufacturing modeling methodology that predicts feature scale, within chip, and wafer level topography. The modeling methodology takes into account etch depth, deposition, and CMP variations across multiple levels in the design, and across multiple process steps within a given design level.
ACCESS THE FULL ARTICLE
Ushasree Katakamsetty, Jansen Chee, Yongfu Li, Colin Hui, Jaime Bravo, Tamba Gbondo-Tugbawa, Brian Lee, Kuang-Han Chen, Aaron Gower-Hall, Sang-Min Han, "Hotspot detection and removal flow using multi-level silicon-calibrated CMP models," Proc. SPIE 9781, Design-Process-Technology Co-optimization for Manufacturability X, 97810K (16 March 2016);