Interlayer design verification methodology using contour image

Minyoung Shim; Seoksan Kim; Sungmin Park; Seiryung Choi; Namjung Kang; Hyunju Sung; Jinwoo Choi; Jaepil Shin; Jaekyun Park; Myoungseob Shim; Hyeongsun Hong; Kyupil Lee

doi:10.1117/12.2218477

16 March 2016 Interlayer design verification methodology using contour image

Minyoung Shim, Seoksan Kim, Sungmin Park, Seiryung Choi, Namjung Kang, Hyunju Sung, Jinwoo Choi, Jaepil Shin, Jaekyun Park, Myoungseob Shim, Hyeongsun Hong, Kyupil Lee

Author Affiliations +

Proceedings Volume 9781, Design-Process-Technology Co-optimization for Manufacturability X; 97810V (2016) https://doi.org/10.1117/12.2218477
Event: SPIE Advanced Lithography, 2016, San Jose, California, United States

Abstract

Memory industry has been pursuing endless shrinking technology which increases fabrication complexity. It poses problems between adjacent layers as well as within a single layer. To verify the interlayer design, we have developed the interlayer design verification methodology using contour image. Our methodology makes it possible to verify interlayer design visually by extracting the contour image from the real patterns. And we can verify interlayer design even during the fabrication process and conduct a non-destructive inspection. Also this methodology provides a statistical analysis of massive measured data. Through this methodology, we can calculate the margin of current interlayer design and suggest the requirement of design.

Citation Download Citation

Minyoung Shim, Seoksan Kim, Sungmin Park, Seiryung Choi, Namjung Kang, Hyunju Sung, Jinwoo Choi, Jaepil Shin, Jaekyun Park, Myoungseob Shim, Hyeongsun Hong, and Kyupil Lee "Interlayer design verification methodology using contour image", Proc. SPIE 9781, Design-Process-Technology Co-optimization for Manufacturability X, 97810V (16 March 2016); https://doi.org/10.1117/12.2218477

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