In this paper, we explain the need to include the etch component during multiple patterning OPC. We also introduce a novel approach for Etch-aware simultaneous Multiple-patterning OPC, where we calibrate and verify a lumped model that includes the combined resist and etch responses. Adding this extra simulation condition during OPC is suitable for full chip processing from a computation intensity point of view. Also, using this model during OPC to predict and correct inter-exposures hot-spots is similar to previously proposed multiple-patterning OPC, yet our proposed approach more accurately corrects post-etch defects too.
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Ayman Hamouda, Dave Power, Mohamed Salama, Ao Chen, "Wafer hotspot prevention using etch aware OPC correction," Proc. SPIE 9781, Design-Process-Technology Co-optimization for Manufacturability X, 978115 (16 March 2016);