23 March 2016 Patterning challenges in advanced device architectures: FinFETs to nanowires
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Abstract
Si FinFET scaling is getting more difficult due to extremely narrow fin width control and power dissipation. Nanowire FETs and high mobility channel are attractive options for CMOS scaling. Nanowire FETs can maintain good electrostatics with relaxed nanowire diameter. High mobility channel can provide good performance at low power operation. However their fin patterning is challenging due to fins consisted of different materials or fragile high mobility material. Controlled etch and strip are necessary for good fin cd and profile control. Fin height increase is a general trend of scaled FinFETs and nanowire FETs, which makes patterning difficult not only in fin, but also in gate, spacer and replacement metal gate. It is important that gate and spacer etch have high selectivity to fins and good cd and profile control even with high aspect ratio of fin and gate. Work function metal gate patterning in scaled replacement metal gate module needs controlled isotropic etch without damaging gate dielectric. SF6 based etch provides sharp N-P boundary and improved gate reliability.
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N. Horiguchi, A. P. Milenin, Z. Tao, H. Hubert, E. Altamirano-Sanchez, A. Veloso, L. Witters, N. Waldron, L.-Å. Ragnarsson, M. S. Kim, Y. Kikuchi, H. Mertens, P. Raghavan, D. Piumi, N. Collaert, K. Barla, A. V.-Y. Thean, "Patterning challenges in advanced device architectures: FinFETs to nanowires", Proc. SPIE 9782, Advanced Etch Technology for Nanopatterning V, 978209 (23 March 2016); doi: 10.1117/12.2220605; https://doi.org/10.1117/12.2220605
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