ASIC-based architecture for the real-time computation of 2D convolution with large kernel size

Rui Shao; Sheng Zhong; Luxin Yan

doi:10.1117/12.2205642

14 December 2015 ASIC-based architecture for the real-time computation of 2D convolution with large kernel size

Rui Shao, Sheng Zhong, Luxin Yan

Proceedings Volume 9814, MIPPR 2015: Parallel Processing of Images and Optimization; and Medical Imaging Processing; 981405 (2015) https://doi.org/10.1117/12.2205642
Event: Ninth International Symposium on Multispectral Image Processing and Pattern Recognition (MIPPR2015), 2015, Enshi, China

Abstract

Bidimensional convolution is a low-level processing algorithm of interest in many areas, but its high computational cost constrains the size of the kernels, especially in real-time embedded systems. This paper presents a hardware architecture for the ASIC-based implementation of 2-D convolution with medium–large kernels. Aiming to improve the efficiency of storage resources on-chip, reducing off-chip bandwidth of these two issues, proposed construction of a data cache reuse. Multi-block SPRAM to cross cached images and the on-chip ping-pong operation takes full advantage of the data convolution calculation reuse, design a new ASIC data scheduling scheme and overall architecture. Experimental results show that the structure can achieve 40× 32 size of template real-time convolution operations, and improve the utilization of on-chip memory bandwidth and on-chip memory resources, the experimental results show that the structure satisfies the conditions to maximize data throughput output , reducing the need for off-chip memory bandwidth.

Citation Download Citation

Rui Shao, Sheng Zhong, and Luxin Yan "ASIC-based architecture for the real-time computation of 2D convolution with large kernel size", Proc. SPIE 9814, MIPPR 2015: Parallel Processing of Images and Optimization; and Medical Imaging Processing, 981405 (14 December 2015); https://doi.org/10.1117/12.2205642

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