The electric simulation models of CMOS devices provided by the foundries are valid at the standard temperature range of -55 to 125°C. These models are not suitable to the design of circuits intended to operate at cryogenic temperatures as is the case of cooled infrared readout circuits. To generate a library of CMOS electric simulation models valid at cryogenic temperatures, the characterization of wide and long CMOS transistors are investigated. The EKV2.6 model, which is an industry-standard compact simulation model for CMOS transistors, is used in this characterization. Due to its relatively small number of parameters the EKV2.6 model is well suited to the parameter extraction procedures when not disposing of an expensive automated parameter extraction system. It is shown that to provide an appropriate IV-characteristic fit to cryogenic temperature range it is sufficient to extract only five parameters - threshold voltage VT0, body effect GAMMA, Fermi potential PHI, transconductance factor KP, and the vertical characteristic field for mobility reduction E0. The proposed approach is tested in a standard 0.35μm/3.3V CMOS technology, employing extraction procedures recommended in the literature. Simulations are made with a BSIM3V3 standard library provided by the foundry changing the temperature parameter and with the generated library. The results are compared with the measurements. As expected, the simulations made with the generated library show a best agreement with the performed measurements at 77K than the simulations with the BSIM3V3 model. The proposed methodology is shown to be particularly effective above strong freeze-out temperature.