12 May 2016 An Implementation of real-time phased array radar fundamental functions on DSP-focused, high performance embedded computing platform
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Abstract
This paper investigates the feasibility of real-time, multiple channel processing of a digital phased array system backend design, with focus on high-performance embedded computing (HPEC) platforms constructed based on general purpose digital signal processor (DSP). Serial RapidIO (SRIO) is used as inter-chip connection backend protocol to support the inter-core communications and parallelisms. Performance benchmark was obtained based on a SRIO system chassis and emulated configuration similar to a field scale demonstrator of Multi-functional Phased Array Radar (MPAR). An interesting aspect of this work is comparison between “raw and low-level” DSP processing and emerging tools that systematically take advantages of the parallelism and multi-core capability, such as OpenCL and OpenMP. Comparisons with other backend HPEC solutions, such as FPGA and GPU, are also provided through analysis and experiments.
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Xining Yu, Yan Zhang, Ankit Patel, Allen Zahrai, Mark Weber, "An Implementation of real-time phased array radar fundamental functions on DSP-focused, high performance embedded computing platform", Proc. SPIE 9829, Radar Sensor Technology XX, 982913 (12 May 2016); doi: 10.1117/12.2224058; https://doi.org/10.1117/12.2224058
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