26 July 2016 The RTE inversion on FPGA aboard the solar orbiter PHI instrument
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Abstract
In this work we propose a multiprocessor architecture to reach high performance in floating point operations by using radiation tolerant FPGA devices, and under narrow time and power constraints. This architecture is used in the PHI instrument that carries out the scientific analysis aboard the ESA’s Solar Orbiter mission. The proposed architecture, in a SIMD flavor, is aimed to be an accelerator within the Data Processing Unit (it is composed by a main Leon processor and two FPGAs) for carrying out the RTE inversion on board the spacecraft using a relatively slow FPGA device – Xilinx XQR4VSX55–. The proposed architecture squeezes the FPGA resources in order to reach the computational requirements and improves the ground-based system performance based on commercial CPUs regarding time and power consumption. In this work we demonstrate the feasibility of using this FPGA devices embedded in the SO/PHI instrument. With that goal in mind, we perform tests to evaluate the scientific results and to measure the processing time and power consumption for carrying out the RTE inversion.
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J. P. Cobos Carrascosa, B. Aparicio del Moral, J. L. Ramos Mas, M. Balaguer, A. C. López Jiménez, J. C. del Toro Iniesta, "The RTE inversion on FPGA aboard the solar orbiter PHI instrument", Proc. SPIE 9913, Software and Cyberinfrastructure for Astronomy IV, 991342 (26 July 2016); doi: 10.1117/12.2232332; https://doi.org/10.1117/12.2232332
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