27 July 2016 Implementation of an FPGA-based DCDS video processor for CCD imaging
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Abstract
Noise modeling of an E2V CCD231 suggested that a weighted double correlated sampler (DCDS) processor could offer small noise improvements at low pixel rates. The model was used to produce synthetic video waveforms that were then processed at various ADC frequencies and analogue bandwidths to identify the best weighting strategy and preamplifier design. An FPGA-based DCDS controller was then built, first to measure the actual CCD noise spectrum and then to verify the earlier theoretical results.
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Simon Tulloch, Simon Tulloch, "Implementation of an FPGA-based DCDS video processor for CCD imaging", Proc. SPIE 9915, High Energy, Optical, and Infrared Detectors for Astronomy VII, 991530 (27 July 2016); doi: 10.1117/12.2240405; https://doi.org/10.1117/12.2240405
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