10 May 2016 Defect avoidance for EUV photomask readiness at the 7 nm node
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Abstract
Several challenges hinder extreme ultraviolet lithography (EUVL) photomask fabrication and its readiness for high volume manufacturing (HVM). The lack in availability of pristine defect-free blanks as well as the absence of a robust mask repair technique mandates defect mitigation through pattern shift for the production of defect-free photomasks. The work presented here provides a comprehensive look at pattern shift implementation to intersect EUV HVM for the 7 nm technology node. An empirical error budget to compensate for measurement variability and errors, based on the latest HVM inspection and write tool capabilities, is first established and then experimentally verified. The validated error budget is applied to 20 representative EUV blanks and pattern shift is performed on fully functional 7 nm node chip designs. The probability of defect-free masks is explored for various layers, including metal, contact, and gate cut layers. From these results, an assessment is made on the current viability of defect-free EUV masks and what is required to construct a complete defect-free EUV mask set.
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Zhengqing John Qi, Zhengqing John Qi, Jed Rankin, Jed Rankin, Eisuke Narita, Eisuke Narita, Masayuki Kagawa, Masayuki Kagawa, "Defect avoidance for EUV photomask readiness at the 7 nm node", Proc. SPIE 9984, Photomask Japan 2016: XXIII Symposium on Photomask and Next-Generation Lithography Mask Technology, 99840Q (10 May 2016); doi: 10.1117/12.2239421; https://doi.org/10.1117/12.2239421
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