This PDF file contains the front matter associated with SPIE Proceedings Volume 9985, including the Title Page, Copyright information, Table of Contents, and Conference Committee listing.

The world’s first high throughput multi-beam mask writers (MBMW) have been realized by upgrading the existing MBMW Alpha and Beta tools with a 10x faster data path. In these tools a multi-beam column provides 262-thousand programmable beams of 20nm beam size. The current density is adjustable up to 1 A/cm², resulting in a total beam current of up to 1 μA. With the upgraded 120 Gbps data path full field 7nm node layouts can be printed in less than 10 hours. This upgrade completes IMS’ first generation of multi-beam mask writers, which is called MBMW-101 and is meeting the requirements of the 7nm technology node.

Multi-beam mask writer is under development to solve the throughput and patterning resolution problems in VSB mask writer. Theoretically, the writing time is appropriate for future design node and the resolution is improved with multi-beam mask writer. Many previous studies show the feasible results of resolution, CD control and registration. Although such technical results of development tool seem to be enough for mass production, there are still many unexpected problems for real mass production. In this report, the technical challenges of multi-beam mask writer are discussed in terms of production and application. The problems and issues are defined based on the performance of current development tool compared with the requirements of mask quality. Using the simulation and experiment, we analyze the specific characteristics of electron beam in multi-beam mask writer scheme. Consequently, we suggest necessary specifications for mass production with multi-beam mask writer in the future.

In Electron Beam Lithography (EBL), the modeling of the Proximity Effects (PE) is the key to successfully print patterns of different size and density at the desired dimension. Although current PE models are increasingly efficient for nominal process conditions, they do not allow covering a broad exposure dose range, which would be interesting for extending the process window, for instance. This paper shows how to improve the accuracy of the dimension estimations of overexposed patterns by EBL by adding a new term to the existing compact model. This advanced compact model was inspired by the chemical mechanisms that activate the acid generator embedded in the resist during the EBL exposure. Most of the existing compact models use the electronic Aerial Image (E AEI) calculated by the convolution product of the patterns geometry with a Point Spread Function (PSF) and extract pattern contours using a threshold value to model the non-linear resist behavior [1]. Here the patterns contours are simulated using an Acid Aerial Image (A AEI) calculated from the initial E_AEI complemented by the Dill transformation [1]. A strong impact is expected at high exposure doses but no changes should occur on patterns exposed close to their nominal dose. The modeling and calibration capabilities of Inscale® software was used to validate the new model with experimental measurements. Calibration and simulations obtained with both standard model and advanced model were compared on a test design. First it shows that after calibration the PSF of the two models are similar, meaning that physics is consistent for both models. The new advanced model allows maintaining the accuracy at nominal dose but increases the overall accuracy by 62 % for a process window of dose with latitude extended up to 20%.

Semiconductor scaling is slowing down because of difficulties of device manufacturing below logic 7nm node generation. Various lithography candidates which include ArF immersion with resolution enhancement technology (like Inversed Lithography technology), Extreme Ultra Violet lithography and Nano Imprint lithography are being developed to address the situation. In such advanced lithography, shot counts of mask patterns are estimated to increase explosively in critical layers, and then it is hoped that multi beam mask writer (MBMW) is released to handle them within realistic write time. However, ArF immersion technology with multiple patterning will continue to be a mainstream lithography solution for most of the layers. Then, the shot counts in less critical layers are estimated to be stable because of the limitation of resolution in ArF immersion technology. Therefore, single beam mask writer (SBMW) can play an important role for mask production still, relative to MBMW. Also the demand of SBMW seems actually strong for the logic 7nm node. To realize this, we have developed a new SBMW, EBM-9500 for mask fabrication in this generation. A newly introduced electron beam source enables higher current density of 1200A/cm². Heating effect correction function has also been newly introduced to satisfy the requirements for both pattern accuracy and throughput. In this paper, we will report the configuration and performance of EBM-9500.

ASML introduced the NXE pellicle concept, a removable pellicle solution that is compatible with current and future patterned mask inspection methods. We will present results of how we have taken the idea from concept to a demonstrated solution enabling the use of EUV pellicle by the industry for high volume manufacturing. We will update on the development of the next generation of pellicle films with higher power capability. Further, we will provide an update on top level requirements for pellicles and external interface requirements needed to support NXE pellicle adoption at a mask shop. Finally, we will present ASML’s pellicle handling equipment to enable pellicle use at mask shops and our NXE pellicle roadmap outlining future improvements.

As for the EUV pellicle, closed pellicle structure with the filters which has fundamentally no penetration path of particles is needed to keep the clean reliability level of photomask equivalent to the current photolithography. We proposed a novel closed EUV pellicle equipped with filters which has not only the particle intrusion prevention but also the ventilation performance. Full-size closed EUV pellicle was fabricated by forming the vent holes in the Si border part and putting the wide filters on the top side of Si border. As the result, we experimentally confirmed the suppression of the membrane deflection under the practical pumping down condition.

EUV lithography insertion is anticipated at the 7 nm node and below; however, defects added to the mask during use is a lingering concern. Defectivity in the scanner is non-zero and an EUV pellicle membrane to protect the mask for high volume manufacturing power levels does not yet exist. The EUV photons are strongly absorbed by all materials. Sibased membranes leverage the low absorption coefficient k value (k = 0.0018 at 13.5 nm) for reasonable transmission, but poly Si becomes fragile and wrinkles during the high temperatures associated with exposure. An alternate approach to high transmission is deploying very thin or porous layers so that there are fewer atoms to absorb light. For example, carbon nanomaterials have a reasonably low k value (k = 0.0069), but are strong enough to be fabricated in very thin layers. Graphene, graphite, carbon-nanosheets and carbon nanotubes are all candidate carbon nanomaterials for this application, but we focus here on carbon nanotubes (CNTs). Our first measurements on CNT films of ~60 nm thick were found to have 96.5% transmission at 13.5 nm. Adding CNT layers also enhanced the strength of a thin SiN membrane significantly. In this paper, critical pellicle metrics will be evaluated in more detail: EUV transmission, bulge test for mechanical strength, emissivity measurements for heat management, and exposure testing in a hydrogen environment.

Multi-tone mask (MTM) consists of more than two layers having different transmittance modulation layers. A novel method is proposed to manufacture a MTM based on two kinds of transmittance modulation materials such as chromium and molybdenum. Different modulation materials cannot be only act as etch-stopper to each other, but also they play a role as a separator between the layers consisted of MTM. Furthermore, clearly classified modulation layers contribute to define one of the targeted transmittance according to different etching process. Especially, a conventional MTM requires three mask writing processes to form three patterns whereas the proposed MTM structure makes it possible to form three patterns by using only two mask writing processes. It is found that the turnaround time of proposed MTM is remarkably decreased as value of 30% compared to that of conventional MTM. MoSi-/Cr-based tri-tone mask configuration having 37, 15, and 0% of transmittance had been demonstrated based on the optimized thin-film conditions. Optical uniformity characteristics were also carried out to evaluate the photomask performance. Consequently, the proposed MTM is not only expected to extend the variation of objective transmittance, but also it is a very promise method for achieving a high performance photo-mask by reducing its fabrication cost.

For protecting mask from debris, EUV pellicle is considered as a most effective solution. EUV pellicle can avoid contamination on mask by covering mask. Usage of EUV pellicle can reduce mask damage caused by contamination but the pellicle involves transmission loss due to absorption of EUV light. To get high transmission, pellicle made with thin thickness but it can be deformed easily due to weak structure. Deformation of pellicle such as wrinkle leads transmission non-uniformity and transmission non-uniformity will involve CD non-uniformity. For real-application at lithography process, the optical study of deformed pellicle is required to avoid degradation of CD uniformity. In this paper, we discuss transmission non-uniformity with various off-axis-illumination (OAI) conditions. Then we studied CD nonuniformity caused by wrinkled pellicle with various patterns. By increasing spatial coherence, transmission nonuniformity is decrease at small wrinkle region. However, transmission non-uniformity variation is independent with illumination conditions at large wrinkle which has large period. Not only wrinkled pellicle imaging but also CD variation caused by non-uniform transmission is also dependent on illumination conditions. In contrast with transmission nonuniformity, CD non-uniformity with high coherent light is smaller than the result with low coherent light. With all of results, we find that the allowable local tilt angle is varied with wrinkle size and illumination conditions and smallest size of allowable local tilt angle is about 250 mrad for both illuminations.

In this paper, we discuss the impact of various noise sources and optical design on defect sensitivity for bright field EUV actinic pattern inspection. The result shows that an optimum pixel size is needed to maximize the defect signal to noise ratio (SNR) to balance the impact of increasing signal strength and photon shot noise from defect signal and the background pattern intensity (mask layout image) and speckle noise from the mask blank roughness. Moreover, we consider defocus showing that the EUV mask phase effect has an asymmetric impact on pattern defect SNR’s throughfocus. The impact of defocus limits inspection performance based on defect SNR. Using critical defect sizes in a case study, we show the defect SNR performance of the limiting case and discuss the possibility to utilize the phase effect of EUV mask absorber to improve the defect SNR by introducing a nominal defocus into the inspection system. A 50% improvement on SNR is achieved by introducing a -50 nm nominal defocus into the bright field inspection system to operate at a higher defect SNR region.

One of the critical issue of EUV lithography is fabrication of defect-free mask. The origin of the defect is a particle inside the multilayer and bump or pit on glass substrate. This type of defect is called a phase defect. If there is a phase defect, the reflection phase is disordered. As a result, the phase structure is printed as a defect on a wafer. Thus, we have developed micro coherent EUV scatterometry microscope (we called micro-CSM) for phase defect characterization. Micro-CSM records scattering signal from a defect directly exposed by focused coherent EUV having a spot size of φ140-nm in diameter. An off-axis-type Fresnel zone plate was employed as a focusing optics. Phase distribution of the defect is reconstructed with the scattering image by the coherent-diffraction-imaging method. We observed actual phase defects in this work. Actual phase defects were on a mask blanks which was the same grade of the pre-production mask of the semiconductor devices. The positions of actual phase defects have been already inspected by the actinic blank inspection tool. And, the actual phase defects have been already observed using an atomic force microscope. A purpose of this work is observation of these actual defects using micro-CSM and comparison of the results.

In this work, the SEMI specification for reticle and pod management (E109) with internal reticle library support has been integrated for the first time on KLA-Tencor’s Teron^TM and TeraScan^TM reticle inspection tools. Manufacturing Execution System scheduling reticle jobs and Automated Material Handling System scheduling to transfer pods simultaneously have also been integrated and tested. GLOBALFOUNDRIES collaboratively worked with KLA-Tencor to successfully implement these capabilities. Both library and non-library scenarios have been demonstrated for comparison in a real production environment resulting in productivity increase of approximately 29% by making use of the library. Reticle re-qualification test cases were used for the comparison in this work.

YieldStar (YS) is an established ASML-built scatterometer that is capable of measuring wafer Critical Dimension (CD), Overlay and Focus. In a recent work, the application range of YS was extended to measure 3D CD patterns on a reticle (pattern CD, height, Side Wall Angle-SWA). The primary motivation for this study came from imaging studies that indicated a need for measuring and controlling reticle 3D topography. CD scanning electron microscope (CD-SEM), Atomic force microscope (AFM), 3D multiple detector SEM (3D-SEM) are the preferred tools for reticle metrology. While these tools serve the industry well, the current research to the impact of reticle 3D involves extensive costs, logistic challenges and increased reticle lead time. YS provides an attractive alternative as it can measure pattern CD, SWA and height in a single measurement and at high throughput. This work demonstrates the capability of YS as a reticle metrology tool.

As the semiconductor industry continues to strive towards high volume manufacturing for EUV, flatness specifications for photomasks have decreased to below 10nm for 2018 production, however the current champion masks being produced report P-V flatness values of roughly ~50nm. Write compensation presents the promising opportunity to mitigate pattern placement errors through the use of geometrically adjusted target patterns which counteract the reticle’s flatness induced distortions and address the differences in chucking mechanisms between e-beam write and electrostatic clamping during scan. Compensation relies on high accuracy flatness data which provides the critical topographical components of the reticle to the write tool. Any errors included in the flatness data file are translated to the pattern during the write process, which has now driven flatness measurement tools to target a 6σ reproducibility <1nm. Using data collected from a 2011 Sematech study on the Alpha Demo Tool, the proposed methodology for write compensation is validated against printed wafer results. Topographic features which lack compensation capability must then be held to stringent specifications in order to limit their contributions to the final image placement error (IPE) at wafer. By understanding the capabilities and limitations of write compensation, it is then possible to shift flatness requirements towards the “non-correctable” portion of the reticle’s profile, potentially relieving polishers from having to adhere to the current single digit flatness specifications.

MEEF, or Mask Error Enhancement Factor, is simply defined as the ratio of the change in printed wafer feature width to the change in mask feature width scaled to wafer level. It is important in chip manufacturing that leads to the amplification of mask errors, creating challenges with both achieving dimensional control tolerances and ensuring defect free masks, as measured by on-wafer image quality. As lithographic imaging continues to be stressed, using lower and lower k1 factor resolution enhancement techniques, the high MEEF areas present on advanced optical masks creates an environment where the need for increased mask defect sensitivity in high-MEEF areas becomes more and more critical. There are multiple approaches to mask inspection that may or may not provide enough sensitivity to detect all wafer-printable defects; the challenge in the application of these techniques is simultaneously maintaining an acceptable level of mask inspectability. The higher the MEEF, the harder the challenge will be to achieve and appropriate level of sensitivity while maintaining inspectability…and to do so on the geometries that matter. The predominant photomask fabrication inspection approach in use today compares the features on the reticle directly with the design database using high-NA optics. This approach has the ability to detect small defects, however, when inspecting aggressive OPC, it can lead to the over-detection of inconsequential, or nuisance defects. To minimize these nuisance detections, changing the sensitivity of the inspection can improve the inspectability of a mask inspected in high-NA mode, however, it leads to the inability to detect subtle, yet wafer-printable defects in High-MEEF geometry, due to the fact that this ‘desense’ must be applied globally. There are also ‘lithography-emulating’ approaches to inspection that use various means to provide high defect sensitivity and the ability to tolerate inconsequential, non-printing defects by using scanner-like conditions to determine which defects are wafer printable. This inspection technique is commonly referred to as being ‘lithography plane’ or ‘litho plane,’ since it’s assessing the mask quality based on how the mask appears to the imaging optics during use, as proposed to traditional ‘reticle plane’ inspection which is comparing the mask only with its target design. Regardless of how the defects are detected, the real question is when should they be detected? For larger technology nodes, defects are considered ‘statistical risks’…i.e., first they have to occur, and then they have to fall in high-MEEF areas in order to be of concern, and be below the detection limits of traditional reticle-plane inspection. In short, the ‘perfect storm’ has to happen in order to miss printable defects using well-optimized traditional inspection approaches. The introduction of lithographic inspection techniques has revealed this statistical game is a much higher risk than originally estimated, in that very subtle waferprintable CD errors typically fall into the desense band for traditional reticle plane inspection. Because printability is largely influenced by MEEF, designs with high-MEEF values are at greater risk of traditional inspection missing printable CD errors. The question is… how high is high… and at what MEEF is optical inspection at the reticle plane sufficient? This paper will provide evaluation results for both reticle-plane and litho-plane inspections as they pertain to varying degrees of MEEF. A newly designed high-MEEF programmed defect test mask, named VAMPIRE, will be introduced. This test mask is based on 7 nm node technology and contains intentionally varying degrees of MEEF as well as a variety of programmed defects in high-MEEF environments…all of which have been verified for defect lithographic significance on a Zeiss AIMS system.

As optical lithography is extended into 10nm and below nodes, advanced designs are becoming a key challenge for mask manufacturers. Techniques including advanced optical proximity correction (OPC) and Inverse Lithography Technology (ILT) result in structures that pose a range of issues across the mask manufacturing process. Among the new challenges are continued shrinking sub-resolution assist features (SRAFs), curvilinear SRAFs, and other complex mask geometries that are counter-intuitive relative to the desired wafer pattern. Considerable capability improvements over current mask making methods are necessary to meet the new requirements particularly regarding minimum feature resolution and pattern fidelity. Advanced processes using the IMS Multi-beam Mask Writer (MBMW) are feasible solutions to these coming challenges. In this paper, Part 2 of our study, we further characterize an MBMW process for 10nm and below logic node mask manufacturing including advanced pattern analysis and write time demonstration.

The introduction of Extreme Ultraviolet Lithography (EUV) as a replacement for multiple patterning is based on improvements of cycle time, yield, and cost. Earlier cost studies have assumed a simple assumption that EUV masks (being more complex with the multilayer coated blank) are not more than three times as expensive as advanced ArFi (ArF immersion) masks. EUV masks are expected to be more expensive during the ramp of the technology because of the added cost of the complex mask blank, the use of EUV specific mask tools, and a ramp of yield learning relative to the more mature technologies. This study concludes that, within a range of scenarios, the hypothesis that EUV mask costs are not more than three times that of advanced ArFi masks is valid and conservative.

Inverse Lithography Technology (ILT) is gaining acceptance as part of a comprehensive OPC solution especially as a repair technique to locally improve process window where conventional OPC does not have enough degrees of freedom to produce acceptable results. [1] Since ILT is significantly more computationally intensive than conventional OPC, a localized application of ILT does not significantly increase OPC cycle time. As ILT methods mature and become more efficient, combined with the availability of huge compute clusters for post tape out data processing, the possibility of full-field ILT OPC could soon become reality. Full-field ILT OPC may provide improved process window and greater layout flexibility as long as multi-patterning methods with 193 nm exposure wavelength remain the primary lithography strategy for advanced technology nodes. Due to limitations of photomask lithography tools that prevent efficient exposure of non-Manhattan shapes, ILT OPC output is typically post-processed to conform to mask MRC rules, rendering the raw all-angle features to a Manhattanized equivalent. Previous comparisons of raw vs Manhattan ILT OPC at earlier nodes have shown that a Manhattanized output can be made to print on wafer with equivalent process window while conforming to mask manufacturing rules.[2,3,4] In this paper we use wafer-level lithography simulation to compare raw vs Manhattanized ILT output based on current advanced nodes and MRC rules. We expand this study to include a mask model to ensure that mask corner rounding effects are considered.

Traditional pupil optimization for horizontal dark field two-bar building blocks yields a dipole matching its local pitch. This classical “rule” guides the placement for the illumination into a pupil area of high contrast and exposure latitude. However under these illumination conditions the feature exhibits an extremely large relative CD Bossung separation limiting its overlapping process window. Here we show experimentally that contrast-aware source optimization is necessary to lift this relative separation. The Tachyon-generated pupil applied is a very close replica of a rigorously obtained asymmetric illumination solution. The latter has emerged out of a study which evidenced that the formation of this rigorous pupil can be traced back to the interdependency of CD Bossung formation and symmetry of the intensity spectrum across the diffraction orders. Compared to standard D90Y and leaf shape illumination, the optimized pupil provides the highest simulated contrast, and experimentally obtained highest depth-of-focus and lowest pattern shift range. Finally we compare the consequences of intensity balancing versus phase aberration minimization across the diffraction orders and conclude that the balancing of the intensity spectrum is the main responsible factor for lifting the feature’s CD Bossung asymmetry and separation.

We present a framework to analyze the performance of optical imaging in a hyper numerical aperture (NA) immersion lithography scanner. We investigate the method to quantify imaging performance by computing upperand lower-bounds on the threshold normalized image log-slope (NILS) and the depth of focus (DOF) in conjunction with the traditional image quality metrics such as the mask error enhancement factor (MEEF) and the linearity for various different pitches and line to space (LS) duty cycles. The effects of the interaction between the light illumination and the feature size are extensively characterized based on the aerial image (AI) behavior in particular for the extreme dipole illumination that is one of the commonly used off-axis illuminations for sub-100nm logic and memory devices, providing resolution near the physical limit of an optical single patterning step. The proposed aerial imaging-based DOF bounds are compared to the results obtained from an experimentally calibrated resist model, and we observed good agreement. In general, the extreme dipole illumination is only optimal for a single particular pitch, therefore understanding the through-pitch imaging performance bound, which depends on the illumination shape, pattern size, and process conditions, is critically important. We find that overall imaging performance varies depending upon the number of diffracted beams passing through the scanner optics. An even number of beams provides very different trends compared to the results from an odd-number of beams. This significant non-linear behavior occurs in certain pitch regions corresponding to 3 beam interference imaging. In this region the imaging performance and the pattern printability become extremely sensitive to the LS duty cycle. In addition, there is a notable tradeoff between the DOF and the NILS that is observed in the problematic 3-beam region and this tradeoff eventually affects the achievable process window (PW). Given the practical real world constraints such as the design rules and target design restrictions, computing upper- and lower-bounds of the through-pitch DOF and NILS will be especially useful for both lithographers and metrology target designers in understanding this complex behavior, as well as helping in the design of optimal targets used for applications including alignment, overlay control, and process control in high volume semiconductor manufacturing.

As the process generation migrate to advanced and smaller dimension or pitch, the mask and resist 3D effects will impact the lithography focus common window severely because of both individual depth-of-focus (iDOF) range decrease and center mismatch. Furthermore, some chemical or thermal factors, such as PEB (Post Exposure Bake) also worsen the usable depth-of-focus (uDOF) performance. So the mismatch of thru-pitch iDOF center should be considered as a lithography process integration issue, and more complicated to partition the 3D effects induced by optical or chemical factors. In order to reduce the impact of 3D effects induced by both optical and chemical issues, and improve iDOF center mismatch, we would like to propose a mask absorber thickness offset approach, which is directly to compensate the iDOF center bias by adjusting mask absorber thickness, for iso, semi-iso or dense characteristics in line, space or via patterns to enlarge common process window, i.e uDOF, which intends to provide similar application as Flexwave[1] (ASML trademark). By the way, since mask absorber thickness offset approach is similar to focus tuning or change on wafer lithography process, it could be acted as the process tuning method of photoresist (PR) profile optimization locally, PR scum improvement in specific patterns or to modulate etching bias to meet process integration request. For mass production consideration, and available material, current att-PSM blank, quartz, MoSi with chrome layer as hard-mask in reticle process, will be implemented in this experiment, i.e. chrome will be kept remaining above partial thru-pitch patterns, and act as the absorber thickness bias in different patterns. And then, from the best focus offset of thru-pitch patterns, the iDOF center shifts could be directly corrected and to enlarge uDOF by increasing the overlap of iDOF. Finally, some negative tone development (NTD) result in line patterns will be demonstrated as well.

We evaluated and compared the i-line 5.2 % Cr based EAPSM and i-line 5.2 % MoSi based EAPSM to find more appropriate material of shifter for FPD. The evaluation items were their CD linearity, phase shift, and optical properties such as transmittance, reflectance, and absorbance under the wavelength range 200-800 nm. Finally, from the results, we performed simulations. The CD linearity and the phase shift were seen as the performances of the same level within all their specifications. The optical properties indicated that the transmittance was higher in the i-line 5.2 % Cr based EAPSM than in i-line 5.2 % MoSi based EAPSM from about 350 nm wavelength, and the reflectance was lower in the iline 5.2 % Cr based EAPSM than in i-line 5.2 % MoSi based EAPSM under the entire wavelength region. From these results, NILS and contrast were simulated between them in 5.0 μm pitch LS pattern and it was found that they did not have a significant difference. Side-lobe effect appeared in both EAPSMs when clear features were closely adjacent under 2.0 μm contact pattern. However, the side-lobe could be removed effectively by adopting Rim type EAPSM. The i-line 5.2 % MoSi based EAPSM may be more suitable for the Rim type EAPSM than the i-line 5.2 % Cr based EAPSM considering their structure and production process of the Rim type EAPSM. It may be appropriate that we use the i-line 5.2 % Cr based EAPSM in LS pattern and the i-line 5.2 % MoSi based EAPSM in contact pattern, because they were almost same level in that performance perspective.

The main source of placement error in maskmaking using electron beam is charging. DISPLACE software provides a method to correct placement errors for any layout, based on a physical model. The charge of a photomask and multiple discharge mechanisms are simulated to find the charge distribution over the mask. The beam deflection is calculated for each location on the mask, creating data for the placement correction. The software considers the mask layout, EBL system setup, resist, and writing order, as well as other factors such as fogging and proximity effects correction. The output of the software is the data for placement correction. Unknown physical parameters such as fogging can be found from calibration experiments. A test layout on a single calibration mask was used to calibrate physical parameters used in the correction model. The extracted model parameters were used to verify the correction. As an ultimate test for the correction, a sophisticated layout was used for verification that was very different from the calibration mask. The placement correction results were predicted by DISPLACE, and the mask was fabricated and measured. A good correlation of the measured and predicted values of the correction all over the mask with the complex pattern confirmed the high accuracy of the charging placement error correction.

One of the main challenges in photomask cleaning is balancing particle removal efficiency (PRE) with pattern damage control. To overcome this challenge, a high frequency megasonic cleaning strategy is implemented. Apart from megasonic frequency and power, photomask surface conditioning also influences cleaning performance. With improved wettability, cleanliness is enhanced while pattern damage risk is simultaneously reduced. Therefore, a particle removal process based on higher megasonic frequencies, combined with proper surface pre-treatment, provides improved cleanliness without the unintended side effects of pattern damage, thus supporting the extension of megasonic cleaning technology into 10nm half pitch (hp) device node and beyond.

Since the introduction of 248 and 193 nm lithography sub-pellicle contamination has been a significant problem and a major contributor to reticle costs and semiconductor yield losses. The most common contaminant identified has been ammonium sulfate commonly called haze, however there have been many other contaminants identified and grouped in the category as haze. In attempts to mitigate the cause of this problem various processes and manufacturing protocols have been put in place to either prevent the problem or identify the source of the problem before there is a negative impact in the wafer fab. In spite of efforts to manage the effects of sub-pellicle contamination in the wafer fab, the problem continues to exist. Over the years we have identified many of the compounds and their sources that exist on the sub-pellicle surface, however one has been elusive. This paper will provide both the identification of this compound and its source.

EUV mask repair techniques have primarily focused on absorber biasing to recover the imaging contrast loss originating from multilayer blank defects, while exploratory efforts have investigated local multilayer modification for compensating any through-focus Bossung asymmetry. The work here evaluates these repair techniques and attempts to expand upon them through finite-difference time-domain (FDTD) simulations. In particular, the possibility of local material deposition as an added repair technique is considered, and the interactions between various compensation strategies and illumination modes are explored. A multilayer defect repair methodology that is non-disruptive to the multilayer stack is introduced for the recovery of both the amplitude loss and phase error originating from native blank defects. The effectiveness of the compensation technique is shown to be independent of the defect type, providing a repair solution that is impartial to the phase offset induced by the multilayer defect. Significant lithographic process window improvements are reported, as compared to conventional absorber-based repair, attributed primarily to the restoration of symmetric printing behavior through defocus. This provides an alternative, viable approach to HVM multilayer defect repair.

According to the 2013 SEMATECH Mask Industry Survey,i roughly half of all photomasks are produced using laser mask pattern generator (“LMPG”) lithography. LMPG lithography can be used for all layers at mature technology nodes, and for many non-critical and semi-critical masks at advanced nodes. The extensive use of multi-patterning at the 14-nm node significantly increases the number of critical mask layers, and the transition in wafer lithography from positive tone resist to negative tone resist at the 14-nm design node enables the switch from advanced binary masks back to attenuated phase shifting masks that require second level writes to remove unwanted chrome. LMPG lithography is typically used for second level writes due to its high productivity, absence of charging effects, and versatile non-actinic alignment capability. As multi-patterning use expands from double to triple patterning and beyond, the number of LMPG second level writes increases correspondingly. The desire to reserve the limited capacity of advanced electron beam writers for use when essential is another factor driving the demand for LMPG capacity. The increasing demand for cost-effective productivity has kept most of the laser mask writers ever manufactured running in production, sometimes long past their projected lifespan, and new writers continue to be built based on hardware developed some years ago.ii The data path is a case in point. While state-ofthe- art when first introduced, hardware-based data path systems are difficult to modify or add new features to meet the changing requirements of the market. As data volumes increase, design styles change, and new uses are found for laser writers, it is useful to consider a replacement for this critical subsystem. The availability of low-cost, high-performance, distributed computer systems combined with highly scalable EDA software lends itself well to creating an advanced data path system. EDA software, in routine production today, scales well to hundreds or even thousands of CPU-cores, offering the potential for virtually unlimited capacity. Features available in EDA software such as sizing, scaling, tone reversal, OPC, MPC, rasterization, and others are easily adapted to the requirements of a data path system. This paper presents the motivation, requirements, design and performance of an advanced, scalable software data path system suitable to support multi-beam laser mask lithography.

Demand for mask process correction (MPC) is growing for leading-edge process nodes. MPC was originally intended to correct CD linearity for narrow assist features difficult to resolve on a photomask without any correction, but it has been extended to main features as process nodes have been shrinking. As past papers have observed, MPC shows improvements in photomask fidelity. Using advanced shape and dose corrections could give more improvements, especially at line-ends and corners. However, there is a dilemma on using such advanced corrections on full mask level because it increases data volume and run time. In addition, write time on variable shaped beam (VSB) writers also increases as the number of shots increases. Optical proximity correction (OPC) care-area defines circuit design locations that require high mask fidelity under mask writing process variations such as energy fluctuation. It is useful for MPC to switch its correction strategy and permit the use of advanced mask correction techniques in those local care-areas where they provide maximum wafer benefits. The use of mask correction techniques tailored to localized post-OPC design can result in similar desired level of data volume, run time, and write time. ASML Brion and NCS have jointly developed a method to feedforward the care-area information from Tachyon LMC to NDE-MPC to provide real benefit for improving both mask writing and wafer printing quality. This paper explains the detail of OPC care-area feedforwarding to MPC between ASML Brion and NCS, and shows the results. In addition, improvements on mask and wafer simulations are also shown. The results indicate that the worst process variation (PV) bands are reduced up to 37% for a 10nm tech node metal case.

In this paper, genetic algorithm (GA) method is applied to both positive and negative Sub Resolution Assist Features (SRAF) insertion rules. Simulation results and wafer data demonstrated that the optimized SRAF rules helped resolve the SRAF printing issues while dramatically improving the process window of the working layer. To find out the best practice to place the SRAF, model-based SRAF (MBSRAF), rule-based SRAF (RBSRAF) with pixelated OPC simulation and RBSRAF with GA method are thoroughly compared. The result shows the apparent advantage of RBSRAF with GA method.

Recent years have seen a fast technical development within the display area. Displays get ever higher pixel density and the pixels get smaller. Current displays have over 800 PPI and market forces will eventually drive for densities of 2000 PPI or higher. The transistor backplanes also get more complex. OLED displays require 4-7 transistors per pixel instead of the typical 1-2 transistors used for LCDs, and they are significantly more sensitive to errors. New large-area maskwriters have been developed for masks used in high volume production of screens for state-of-theart smartphones. Redesigned laser optics with higher NA and lower aberrations improve resolution and CD uniformity and reduce mura effects. The number of beams has been increased to maintain the throughput despite the higher writing resolution. OLED displays are highly sensitive to placement errors and registration in the writers has been improved. To verify the registration of produced masks a separate metrology system has been developed. The metrology system is self-calibrated to high accuracy. The calibration is repeatable across machines and sites using Z-correction. The repeatability of the coordinate system makes it possible to standardize the coordinate system across an entire supply chain or indeed across the entire industry. In-house metrology is a commercial necessity for high-end mask shop, but also the users of the masks, the panel makers, would benefit from having in-house metrology. It would act as the reference for their mask suppliers, give better predictive and post mortem diagnostic power for the panel process, and the metrology could be used to characterize and improve the entire production loop from data to panel.

Imprint lithography has been shown to be an effective technique for replication of nano-scale features. Jet and Flash* Imprint Lithography (J-FIL*) involves the field-by-field deposition and exposure of a low viscosity resist deposited by jetting technology onto the substrate. The patterned mask is lowered into the fluid which then quickly flows into the relief patterns in the mask by capillary action. Following this filling step, the resist is crosslinked under UV radiation, and then the mask is removed, leaving a patterned resist on the substrate. There are many criteria that determine whether a particular technology is ready for wafer manufacturing. Defectivity and mask life play a significant role relative to meeting the cost of ownership (CoO) requirements in the production of semiconductor devices. Hard particles on a wafer or mask create the possibility of inducing a permanent defect on the mask that can impact device yield and mask life. By using material methods to reduce particle shedding and by introducing an air curtain system, the lifetime of both the master mask and the replica mask can be extended. In this work, we report results that demonstrate a path towards achieving mask lifetimes of better than 1000 wafers. On the mask side, a new replication tool, the FPA-1100 NR2 is introduced. Mask replication is required for nanoimprint lithography (NIL), and criteria that are crucial to the success of a replication platform include both particle control, resolution and image placement accuracy. In this paper we discuss the progress made in both feature resolution and in meeting the image placement specification for replica masks.

6-inch size (known as 6025QZ) binary Cr mask is widely used in the semiconductor lithography for over 20years. Recently for the 450mm wafer process, high grade 9-inch size mask is expected. For this application, we have studied and developed prototyping 9-inch size PSM KrF and ArF mask blanks. This time we will explain these PSM mask blanks status.

In order to enable the large-area patterning of micro-fabrication, constant intensity will be required to the mold material. Then, we have deposited the sample was subjected to a chemical synthesis in different hydroxy propyl cellulose (HPC) viscosity, we evaluated its transferability and optical transparency. As a result of gel permeation chromatography system (GPC) measurement, we confirmed that high viscosity sample was high molecular weight in the two types of HPC with different viscosity. Further, we will produce a film with the sample, we evaluated the transfer and light permeability of the film. In the evaluation of transfer properties, Regardless of the level of the viscosity of the HPC of the main raw material, the shape of the master silicon template(5μm line and space) had been transferred to the HPC template. Moreover in the evaluation of optical transparency, HPC template had about 60% of the light transmittance in the 365nm wavelength. The sample have a possibility to improve the strength to be polymerized, and a high optical transparency, it used in this study is expected to be a mold material for UV nano-imprint lithography.

Over time mask makers have been driven to low sensitivity e-beam resist materials to meet lithographic patterning needs. For 7-nm logic node, resolution enhancement techniques continue to evolve bringing more complexity on mask and additional mask builds per layer. As demonstrated in literature, low sensitivity materials are needed for low line edge roughness (LER) but impact write tool through put. In characterizing resist sensitivity for 7-nm, we explore more broadly what advantages and disadvantages moving to lower sensitivity resist materials brings, where LER, critical dimension uniformity, resolution, fogging, image placement, and write time results and trends are presented. In this paper, resist material performance are reported for sensitivities ranging from 20 to 130 μC/cm² at 50% proximity effect correction, where the exposure will be using a single beam platform. Materials examined include negative tone resist types with chemical amplification and positive tone without chemical amplification focusing on overall trends for 7-nm e-beam resist performance.

EUV pellicle with very thin thickness is significantly affected when external forces are applied. The mechanical forces such as chamber-pellicle pressure difference and stage acceleration cause the mechanical stress in pellicle. We investigated the maximum stress that can be induced by the pressure difference for various materials by using finite element method (FEM). We also used theoretical model and FEM for predicting the pellicle deformation. Our results show the mechanical deformation and the stress of full size (152 × 120 mm²) pellicle with 50 nm thickness, and the influence of the pellicle is increased with larger pressure difference. We also studied the maximum stress caused by the acceleration force of the scanner. The full size pellicle is greatly influenced with the specific pulse width causing resonance. Our study indicates that mechanical stress with acceleration is very small and can be ignored.

In this study, we examine exposure characteristics of a positive tone electron beam resist consisting of methyl α- chloroacrylate and α-methylstyrene by changing the development process conditions. 25/25 nm and 30/30 nm line-andspace (L/S) patterns (design value) are developed in amyl and heptyl acetates. The resist patterns developed at 0ºC for 120 s show the better shapes having the vertical sidewalls than those developed at 22 °C for 60 s. The dose margins of pattern formation for 0°C development become wider, although the sensitivities are lower. The effect of post exposure baking (PEB) on exposure characteristics is also investigated. Adding PEB process performed at 120°C for 2 min, the dose margin also becomes wider although the sensitivity is lower. 20/20 nm L/S patterns are fabricated by using PEB and/or 0°C development. Though the required exposure dose is larger, the resist pattern is improved by PEB and/or 0°C development. The formation of 35 nm pitch pattern is also presented.

As the process node becomes more advanced, the accuracy and precision in OPC pattern CD are required in mask manufacturing. CD SEM is an essential tool to confirm the mask quality such as CD control, CD uniformity and CD mean to target (MTT). Unfortunately, in some cases of arbitrary enclosed patterns or aggressive OPC patterns, for instance, line with tiny jogs and curvilinear SRAF, CD variation depending on region of interest (ROI) is a very serious problem in mask CD control, even it decreases the wafer yield. For overcoming this situation, the 2-dimensional (2D) method by Holon is adopted. In this paper, we summarize the comparisons of error budget between conventional (1D) and 2D data using CD SEM and the CD performance between mask and wafer by complex OPC patterns including ILT features.

In semiconductor manufacturing, as the design rule has decreased, the ITRS roadmap requires crucial tighter critical dimension (CD) control. CD uniformity is one of the necessary parameters to assure good performance and reliable functionality of any integrated circuit (IC) [1] [2], and towards the advanced technology nodes, it is a challenge to control CD uniformity well. The study of corresponding CD Uniformity by tuning Post-Exposure bake (PEB) and develop process has some significant progress[3], but CD side to side error happening to some line/space pattern are still found in practical application, and the error has approached to over the uniformity tolerance. After details analysis, even though use several developer types, the CD side to side error has not been found significant relationship to the developing. In addition, it is impossible to correct the CD side to side error by electron beam correction as such error does not appear in all Line/Space pattern masks. In this paper the root cause of CD side to side error is analyzed and the PEB module process are optimized as a main factor for improvement of CD side to side error.

Actinic mask inspection for EUV lithography with targeted specifications of resolution, sensitivity, and throughput remains a big hurdle for the successful insertion of EUVL into high volume manufacturing and effective solutions are needed to address this. We present a method for actinic mask inspection based on scanning coherent scattering microscopy. In this method, the mask is scanned with an EUV beam of relatively small spot size and the scattered light is recorded with a pixel detector. Customized algorithms reconstruct the aerial image by iteratively solving the phaseproblem using over-determined diffraction data gathered by scanning across the specimen with a finite illumination. This approach provides both phase and amplitude of actinic aerial images of the mask with high resolution without the need to use high NA (numerical aperture) lenses. Futher, we describe a reflective mode EUV mask scanning lensless imaging tool (RESCAN), which was installed at the XIL-II beamline and later at the SIM beamline of the Swiss Light Source and show reconstructed aerial images down to 10 nm (on-wafer) resolution. As a complementary method, the a-priori knowledge of the sample is employed to identify potential defect sites by analyzing the diffraction patterns. In this method, the recorded diffraction patterns are compared with the die or database data (i.e. previously measured or calculated diffraction data from the defect-free mask layout respectively) and their difference is interpreted as the defect signal. Dynamic software filtering helps to suppress the strong diffraction from defect-free structures and allows registration of faint defects with high sensitivity. Here, we discuss the basic principles of these Fourier domain techniques and its potential for actinic mask inspection with high signal-to-noise ratio and high throughput.

In the mask shop the challenges associated with today’s advanced technology nodes, both technical and economic, are becoming increasingly difficult. The constant drive to continue shrinking features means more masks per device, smaller manufacturing tolerances and more complexity along the manufacturing line with respect to the number of manufacturing steps required. Furthermore, the extremely competitive nature of the industry makes it critical for mask shops to optimize asset utilization and processes in order to maximize their competitive advantage and, in the end, profitability. Full maximization of profitability in such a complex and technologically sophisticated environment simply cannot be achieved without the use of smart automation. Smart automation allows productivity to be maximized through better asset utilization and process optimization. Reliability is improved through the minimization of manual interactions leading to fewer human error contributions and a more efficient manufacturing line. In addition to these improvements in productivity and reliability, extra value can be added through the collection and cross-verification of data from multiple sources which provides more information about our products and processes. When it comes to handling mask defects, for instance, the process consists largely of time consuming manual interactions that are error prone and often require quick decisions from operators and engineers who are under pressure. The handling of defects itself is a multiple step process consisting of several iterations of inspection, disposition, repair, review and cleaning steps. Smaller manufacturing tolerances and features with higher complexity contribute to a higher number of defects which must be handled as well as a higher level of complexity. In this paper the recent efforts undertaken by ZEISS to provide solutions which address these challenges, particularly those associated with defectivity, will be presented. From automation of aerial image analysis to the use of data driven decision making to predict and propose the optimized back end of line process flow, productivity and reliability improvements are targeted by smart automation. Additionally the generation of the ideal aerial image from the design and several repair enhancement features offer additional capabilities to improve the efficiency and yield associated with defect handling.

According to the design rule shrinkage, more precise control of mask CD, including mean to target and uniformity, is required in lithography process. Since dry etching is one of the most critical processes to determine CD qualities in photomask, optical emission spectroscopy (OES) to monitor plasma status during dry etching process could be useful. However, it is not possible to obtain distributional information of plasma with a conventional OES tool because the OES acquires totally integrated signals of light from the chamber. To overcome the limit of OES, we set up a spatially resolved (SR)-OES tool and measure the distribution of radicals in plasma during dry etch process. The SR-OES consists of a series of lenses, apertures, and a pinhole as a spatial filter which enable us to focus on certain area in the chamber, to extract the emitted light from plasma, and to perform the spectroscopic analysis. The Argon based actinometry combined with SR-OES shows spatially distinguished peaks related to the etch rate of Chromium on photomask. In this paper, we present experimental results of SR-OES installed on a commercial photomask dry etcher and discuss its practical effectiveness by correlation of the results with chamber etch rate.

To review phase and amplitude defect on extreme ultraviolet (EUV) mask with EUV intensity and phase contrast, we have developed the micro coherent EUV scatterometry microscope (micro-CSM). A coherent EUV beam was focused on a defect using a Fresnel zoneplate, where the illumination size was 140 nm diameter. Diffraction from the defect was captured by an EUV CCD camera directly. The diffraction signal was depended on the zoneplate focus, where the defect signal was efficiently detected at a best focus position. To review an actual EUV mask that has no focus-alignment pattern on surface, we developed a focusing method using a speckle signal.

Next-generation lithography based on EUV continues to move forward to high-volume manufacturing. Given the technical challenges and the throughput concerns a hybrid approach with 193 nm immersion lithography is expected, at least in the initial state. Due to the increasing complexity at smaller nodes a multitude of different masks, both DUV (193 nm) and EUV (13.5 nm) reticles, will then be required in the lithography process-flow. The individual registration of each mask and the resulting overlay error are of crucial importance in order to ensure proper functionality of the chips. While registration and overlay metrology on DUV masks has been the standard for decades, this has yet to be demonstrated on EUV masks. Past generations of mask registration tools were not necessarily limited in their tool stability, but in their resolution capabilities. The scope of this work is an image placement investigation of high-end EUV masks together with a registration and resolution performance qualification. For this we employ a new generation registration metrology system embedded in a production environment for full-spec EUV masks. This paper presents excellent registration performance not only on standard overlay markers but also on more sophisticated e-beam calibration patterns.

It is known that the photomask substrate deflects when the mask is set on the frame and the deflection is an obstacle to light exposure. In this study, we introduce “the bending mask” to cancel out the deflection. The surface of the bending mask has the height distribution in advance to cancel out the deflection, owing to Nikon’s accurate polishing technology and Nikon’s accurate measurement machine.

Two different mask inspection techniques are developed and compared for 14 nm node and beyond photomasks, High resolution and Litho-based inspection. High resolution inspection is the general inspection method in which a 19x nm wavelength laser is used with the High NA inspection optics. Litho-based inspection is a new inspection technology. This inspection uses the wafer lithography information, and as such, this method has automatic defect classification capability which is based on wafer printability. Both High resolution and Litho-based inspection methods are compared using 14 nm and 7 nm node programmed defect and production design masks. The defect sensitivity and mask inspectability is compared, in addition to comparing the defect classification and throughput. Additionally, the Cost / Infrastructure comparison is analyzed and the impact of each inspection method is discussed.

In the semiconductor IC manufacturing industry, challenges associated with producing defect-free photomasks have been dramatically increasing. At the 10nm technology node, since the 193nm immersion scanner numerical aperture has remained the same 1.35 as in previous nodes, more multi-patterning and aggressive SMO illumination sources are being used to effectively print smaller feature CDs and pitches. To accommodate such specialized sources, more model-based mask OPC and ILT have been used making mask designs very complicated. This in turn makes mask manufacturing very challenging especially for the defect inspection, repair, and metrology processes that need to guarantee defect-free masks. Over the past few years, considerable innovation have been made in the areas of defect inspection and disposition that has ensured continued predictability of mask quality to wafer and final chip yields. The accurate disposition of each mask defect before and after repair has been facilitated by a suite of automated applications such as ADC, LPR, RPG, AIA, etc. that work together with the inspection, repair, and metrology tools and effectively also provide the best possible utilization of the tool capability, capacity and operator resources. In this paper we introduce a new consolidated applications platform called the Reticle Decision Center (RDC) which hosts all these supporting software applications on a centralized server with direct connectivity to mask inspection, repair, metrology tools and more. The paper details how the RDC server is architected to host any application in its native operating system environment and provides for high availability with automatic failover and redundancy. The server along with its host of applications has been tightly integrated with KLA-Tencor’s Teron mask inspectors. The paper concludes with showing benefits realized in mask cycle-time and yield as a result of implementing RDC into a high-volume 10nm mask-shop production line.

TNO is building EBL2: a laboratory EUV exposure system capable of operating at high broad band EUV powers and intensities, in which XPS analysis of exposed samples is possible without breaking vacuum. Its goal is to accelerate the development and testing of EUV optics and components by providing a publicly accessible exposure and analysis facility. The system can accept a range of sample sizes, including standard EUV reticles with or without pellicles. In the beam line, EUV masks and other samples can be exposed to EUV radiation in a controlled environment that is representative of actual operating conditions. This contribution will describe the design of the EUV beam line.

As device manufacturers progress through advanced technology nodes, limitations in standard 1-dimensional (1D) mask Critical Dimension (CD) metrics are becoming apparent. Historically, 1D metrics such as Mean to Target (MTT) and CD Uniformity (CDU) have been adequate for end users to evaluate and predict the mask impact on the wafer process. However, the wafer lithographer’s process margin is shrinking at advanced nodes to a point that the classical mask CD metrics are no longer adequate to gauge the mask contribution to wafer process error. For example, wafer CDU error at advanced nodes is impacted by mask factors such as 3-dimensional (3D) effects and mask pattern fidelity on subresolution assist features (SRAFs) used in Optical Proximity Correction (OPC) models of ever-increasing complexity. These items are not quantifiable with the 1D metrology techniques of today. Likewise, the mask maker needs advanced characterization methods in order to optimize the mask process to meet the wafer lithographer’s needs. These advanced characterization metrics are what is needed to harmonize mask and wafer processes for enhanced wafer hot spot analysis. In this paper, we study advanced mask pattern characterization techniques and their correlation with modeled wafer performance.

One of the key challenges of photomask manufacture is to achieve defect-free masks. Clean and repair has been applied to manage defects and particles on the mask imported during manufacturing processes. Since photomask patterns become smaller and more complicated as integrated circuit (IC) scaling to 28 nm node and below, the increasingly importance of mask quality compels us continuously research on more effective defect treatment solutions, to achieve mask yield enhancement and on-schedule delivery. In this paper, we would like to introduce new approaches of defect management with dry treatment assistance, according to particular defect types. One is using plasma etching gases of Cl2/O2 to change the properties of glue compounds adhering to the mask surface, and make them removed by conventional cleaning. Another is the application of O2 plasma dry treatment for the benefit of alleviation on scan damage phenomenon, which comes from contamination on the scan area due to excessive repair cycles.

High pressure carbon dioxide provides a very effective alternative for cleaning integrated circuits and masks. This great cleaning ability is due to CO2 having the physical characteristics of both a liquid and a gas: like a gas, it diffuses rapidly, has near zero surface tension, very low viscosity and thus penetrates easily into mask features or deep wafer trenches and vias. As a liquid it can be utilized to clean particles and to solvate other chemicals such as alcohols and fluorinated hydrocarbons. This paper covers the analytical tests and characterizations carried out to assess impurity removal from 3.0 N CO₂ (beverage grade) for its final utilization in mask cleaning applications.

Wet photomask cleaning relies on megasonic agitation to enhance the process, but there are many challenges to reliably maximize particle removal efficiency (PRE) and minimize damage. With the shift to pellicle-free EUV masks, photomask processes are more vulnerable to contamination, increasing the urgency to improve the cleaning process. This difficulty is largely due to the unavailability of appropriate measurement of the acoustic field. Typically all that is known about the acoustic output is the driving frequency and the electric power delivered to a transducer, both global parameters that tell little about the field distribution over the substrate, the actual amplitude of the sound at the substrate, or the levels of cavitation (stable and transient) present at the substrate.

The ever increasing pattern densities and design complexities make the tuning of optical proximity correction (OPC) recipes more challenging. There are various recipe tuning methods to meet the challenge, such as genetic algorithm (GA), simulated annealing, and OPC software vendor provided recipe optimizers. However, these methodologies usually only consider edge placement errors (EPEs). Therefore, these techniques may not provide adequate freedom to solve unique problems at special geometries, for example bridge, pinch, and process variation band related violations at complex 2D geometries. This paper introduces a general methodology to fix specific problems identified at the OPC verification stage and demonstrates its successful application to two test-cases. The algorithm and method of the automatic scoring system is introduced in order to identify and prioritize the problems that need to be fixed based on severity, with the POR recipe score used as the baseline reference. A GA optimizer, whose objective function is based on the scoring system, is applied to tune the OPC recipe parameters to optimum condition after generations of selections. The GA optimized recipe would be compared to existing recipe to quantify the amount of improvement. This technique was subsequently applied to eliminate certain chronic OPC verification problems which were encountered in the past. Though the benefits have been demonstrated for limited test cases, employing this technique more universally will enable users to efficiently reduce the number of OPC verification violations and provide robust OPC solutions.

One of the major challenges of optical proximity correction (OPC) models is to maximize the coverage of real design features using sampling pattern. Normally, OPC model building is based on 1-D and 2-D test patterns with systematically changing pitches alignment with design rules. However, those features with different optical and geometric properties will generate weak-points where OPC simulation cannot precisely predict resist contours on wafer due to the nature of infinite IC designs and limited number of model test patterns. In this paper, optical property data of real design features were collected from full chips and classified to compare with the same kind of data from OPC test patterns. Therefore sample coverage could be visually mapped according to different optical properties. Design features, which are out of OPC capability, were distinguished by their optical properties and marked as weak-points. New patterns with similar optical properties would be added into model build site-list. Further, an alternative and more efficient method was created in this paper to improve the treatment of issue features and remove weak-points without rebuilding models. Since certain classification of optical properties will generate weak-points, an OPC-integrated repair algorithm was developed and implemented to scan full chip for optical properties, locate those features and then optimize OPC treatment or apply precise sizing on site. This is a named “in-situ” weak-point improvement flow which includes issue feature definition, allocation in full chip and real-time improvement.

As technology shrinks, the requirements placed on the post-OPC solution become so exacting that even small residual optical effects are significant. Simultaneously minimizing rippling and corner rounding cannot be accom- plished in parallel in wafer patterning especially when complex asymmetric pixelated sources are used. While either effect can be moderated by accurate application of optical proximity correction, they are both charac- teristic of unfiltered diffraction due to asymmetric illumination or design geometry and will remain inherent. Corrections that over emphasize reduced corner-rounding necessarily sacrifice edge convergence, resulting in a standing wave or unacceptable rippling along an entire edge. OPC can be used to reduce the magnitude of this rippling, but fragment placing is extremely critical. In this paper, we discuss optimized OPC fragmentation that offers balanced consideration to suppressing rippling and minimizing corner rounding. Specifically, we correlate design shapes with simulated post-OPC contours to account for design geometry-dependent rippling signature given existing illumination conditions. In contrast to adaptive fragmentation that relies on multiple iterations of simulation of intensity extrema redistribution, our method predicts the optimum contour as allowed by process and fragments the mask accordingly. The maximum imaging curvature resolvable by process coupled with the rippling signature, gives rise to the exact locations of the inflection points of the wafer contour. From there we achieve the best correction results by segmenting edges at the inflection points.

As technology advances into deep submicron nodes, the mask manufacturing process accuracy become more important. Mask Process Correction (MPC) has been transitioning from Rules-Based Mask Process correction to Model-Based Mask Process Correction mode. MPC is a subsequent step to OPC, where additional perturbation is applied to the mask shapes to correct for the mask manufacturing process. Shifting towards full model-based MPC is driven mainly by the accuracy requirements in advanced technology nodes, both for DUV and EUV processes. In the current state-of-the-art MPC process, MPC is completely decoupled from OPC, where each of them assumes that the other is executing perfectly. However, this decoupling is not suitable anymore due to the limited tolerance in the mask CDU budget and the increased wafer CDU requirements required from OPC. It is becoming more important to reduce any systematic mask errors, especially where they matter the most. In this work, we present a new combined-verification methodology that allows testing the combined effect of mask process and lithography process together and judging the final wafer patterning quality. This has the potential to intercept risks due to superposition of OPC and MPC correction residual errors, and capturing and correcting such a previously hidden source of patterning degradation.