The high demand for AI services in conjunction with a dramatic chip shortage along with technology leaps such as 5/6G networks, cybersecurity threats, and quantum algorithms have resurrected a R&D push for advanced information processing and computing capability. To address this demand and explore novel technology roadmaps, unique opportunities exist, for example, given by algorithmic parallelism of digital-analog hybrid non-van Neuman accelerators. Especially photonic-electronic ASIC compute paradigms hold promise to enable non-iterative O(1) runtime complexity, ps-short latency, and TOPS/W throughputs. This opens prospects for next-generation hardware both for AI cloud services but also for accelerating edge computing such as enabled by compact and efficient PIC-CMOS co-designs pushing the SWAP envelope. As both a professor and a co-founder of a deep-tech venture, in this seminar I will share my insights on fundamental complexity scaling and algorithm-hardware homomorphism on the one hand, and system-level synergies and co-design optimization strategies on the other. I will introduce a novel photonic RAM capable of zero-static power consumption suitable for edge applications and a mixed-signal tensor core accelerator leveraging parallelism. Beyond matrix-matrix multiplication acceleration, I will show how convolutions can be accelerated as simple dot-product multiplications in the Fourier domain and using display light technology enables 1000x1000 matrix convolutions at 100us latency, or about 10x faster than today’s GPUs. Finally, I will share latest opto-electronic device work such as 20Gbps ITO-based modulators that are 1,000x more compact than Silicon and LN modulators, and discuss scaling-length-theory slot-detectors featuring zero-bias detector and low NEPs.
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