High-k, Metal-Gate FinFET CMOS Manufacturing Process

doi:10.1117/3.2234473.ch3

Book: 3D IC Devices, Technologies, and Manufacturing

Author(s): Hong Xiao

Published: 2016

https://doi.org/10.1117/3.2234473.ch3

Author Affiliations +

Abstract

In the so-called “good old days,” the IC technology-node scaling of each generation always brought both higher device density and better device performance. When CMOS IC developed from the 90-nm to 65-nm node, the scaling did not improve the device performance: it only increased the device density. The main reason for this change is the thickness of the gate oxide can no longer be scaled down due to the leakage caused by the tunneling effect.