The edges of resist line patterns are never completely straight; they invariably show deviations from linearity, which is called line-edge roughness (LER). LER may be derived from pattern roughness in the mask, statistical variations in dose along the line edge, or from the chemical properties of the resist. Variation in the width of a line determines its line-width roughness (LWR). LER and LWR are two of the key parameters that determine device performance. Figure 10.1 shows how a single line can be a gate for multiple transistors. Low-frequency variations in LWR can lead to a different gate length for each transistor. These variations, in turn, cause threshold voltage variations between transistors in the same chip. LWR with periodicities shorter than the gate width can result in problems with leakage current. Experimental results show that leakage current increases exponentially with LWR. For devices fabricated at the 65-nm node, LWR (3Ï) < 8% of gate CD leads to < 1% performance degradation, while LWR (3Ï) < 10% of gate CD leads to < 2% of performance degradation. Based on this analysis, the ITRS requires that the low-frequency portion of the LWR be less than 8% of its CD. For the 45-nm half-pitch node, ITRS requires a LWR of 2.4 nm (3Ï).
In this chapter, lithographic processes and materials will be analyzed to identify the root causes of LER and LWR within printed features. LER and LWR can be improved through optimization of process parameters and selection of the resist materials. In addition, the roughness can be further reduced by smoothing of the resist patterns after development. These âsmoothing processesâ will be summarized and assessed. Resist patterns are transferred to substrates using plasma etch processes. The LER and the LWR of final etched patterns are what actually determine device performance. The extent to which roughness is transferred from the resist pattern to the substrate during the etch process will also be discussed in this chapter.
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