Access to SPIE eBooks is limited to subscribing institutions. Access is not available as part of an individual subscription. However, books can be purchased on SPIE.Org
Chapter 28:
The Intimate Integration of Photonics and Electronics
Editor(s): Ari T. Friberg; René Dändliker
Author(s): Krishnamoorthy, Ashok V.
Abstract
It is evident that computing and switching performance must continue to scale to meet the growing proliferation of computing and communications capability and the reduced price per performance expected from systems manufacturers. Indeed, we have already witnessed over five orders of magnitude improvement in compute performance-per-dollar over the last three decades, well in excess of the improvements delivered by technology scaling alone. In fact, the demand from applications is underserved by Moore's law, and requires continued scaling and improvements in efficiencies at the system level. Examples of such applications include content servers and high-performance computing. For reasons that include hiding memory and wire latency, reducing power dissipation, and managing design complexity, it is now evident that multi-core, multi-threaded processors are necessary for continued scaling of microprocessor performance. But this architectural scaling of processors alone is insufficient to meet all application requirements. System limitations in interconnect power, bandwidth, and density threaten to mask the benefits of improved chip performance, and hinder our ability to create large, power-efficient machines with optimal bisection bandwidth and adequate performance on critical performance benchmarks. For instance, high-performance computing (HPC) systems require sophisticated architectures for optimizing an increased number of processor-memory units, lower latency signaling between chips, and larger system bisection bandwidths for communication. Currently, the top HPC systems have bisection bandwidths between 1 and 10Tbps and next-generation systems are looking for 10–100× improvements in bandwidth. Relying on current and soon-to-be-available optical interconnect modules, one can design enough system bandwidth to enable optical interconnection of modest arrays of processor∕memory units. Simply scaling such system architectures would necessitate vast numbers of optical modules and fiber optic cables. Among the issues of concern in such systems are ways to increase the link data rate while maintaining low cost and high overall system reliability. We believe that techniques that increase the number of effective channels using dense integration of photonic devices with silicon, combined with WDM and multi-level encoding to increase the number of multiplexed optical data channels per optical waveguide will be key. By virtue of its abilities to achieve dense integration, promote electrical-optical symbiosis, utilize wafer-scale silicon manufacturing, achieve WDM and other encoding techniques, photonic interconnects appear to be a scalable interconnect candidate. In this article, we will review some technology examples and opportunities for high-density optical interconnects.
Online access to SPIE eBooks is limited to subscribing institutions.
CHAPTER 28
18 PAGES


SHARE
Back to Top